目的：用VHDL文本输入法设计并实现一个一位半加器。

程序（使用quartus II软件进行编写）

library ieee;
use ieee.std_logic_1164.all;

entity add1_half is
	port(
		Ai,Bi		:in std_logic;
		So,Co		:out std_logic		--So半加和,Co进位输出
		);
end add1_half;

architecture behave of add1_half is
begin
	process(Ai,Bi)
	begin
		So <= Ai xor Bi;
		Co <= Ai and Bi;
	end process;
end behave;		

 仿真波形图

1.真值表

2.逻辑电路

3.端口

4.VHDL语言
4.1.表达1：

library ieee;
use ieee.std_logic_1164.all;

entity h_adder is    
	port (a,b:in STD_LOGIC;
		   co,so:out STD_LOGIC);
end h_adder;

architecture fh of h_adder is
signal sel:STD_LOGIC_VECTOR(1 downto 0);
  begin
    sel <= a&b;
	 process(sel)
	     begin
		case sel is
		    when "00"=>so<='0';co<='0';
			 when "01"=>so<='1';co<='0';
			 when "10"=>so<='1';co<='0';
			 when "11"=>so<='0';co<='1';
			 when others=>null;
		end case;
	 end process;
end fh;

4.2表达2：

library ieee;
use ieee.std_logic_1164.all;

entity h_adder is    
	port (a,b:in STD_LOGIC;
		   co,so:out STD_LOGIC);
end h_adder;

architecture fh of h_adder is
begin
  so <= not(a xor (not b));
  co <= a and b;
end fh;

选了FPGA的课记录一下怎么搭建工程免得忘了

1、先创建工程

然后记得选ISim 要不然等会仿真的时候会让你使用modelsim的仿真器

完成创建 Finish

2、添加模块

选择new source

然后 VHDL Module

接着输入下面的信息

3、编写VHDL代码

输入以下代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HalfAdder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           carry : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end HalfAdder;

architecture Behavioral of HalfAdder is

begin
carry <= a and b;
sum <= a xor b;

end Behavioral;

检查语法

检查语法  check syntax

view RTL Schematic 

双击上面那个 RTL Schematic   可以查看里面的原件    确认没问题后就 开始仿真

4、仿真

design 那里选择 simulation

New Source

创建teset bench

然后写仿真的test bench   

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT HalfAdder
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         carry : OUT  std_logic;
         sum : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';

 	--Outputs
   signal carry : std_logic;
   signal sum : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: HalfAdder PORT MAP (
          a => a,
          b => b,
          carry => carry,
          sum => sum
        );

   -- Clock process definitions


   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		a <= '0';
		b <= '0';
		wait for 100 ns;
		a <= '0';
		b <= '1';
		wait for 100 ns;
		a <= '1';
		b <= '0';
		wait for 100 ns;
		a <= '1';
		b <= '1';
		wait for 100 ns;
			


      -- insert stimulus here 

      wait;
   end process;

END;

确认语法

开始仿真

出来如下界面

在ISim 下面输入 run 500 出现如下波形  确认仿真结果以后  仿真结束。