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  • msm8953 gpio map

    2020-03-06 16:21:58
    msm8953 gpio map
  • 高通MSM8953资料.rar

    2020-11-17 16:40:03
    高通MSM8953资料.rar
  • 高通 MSM8953 spec

    2019-01-03 16:13:13
    高通MSM8953的device specification。The MSM™device uses the advanced 14 nm FinFET process for lower active power dissipation and faster peak CPU performance. It includes a customized 64-bit ARM  ...
  • 高通 MSM8953 datasheet device spec MSM8953 datasheet device spec
  • msm8953 uart配置

    2020-06-11 09:30:10
    1.msm8953.dtsi 中添加code 2. msm8953-pinctrl.dtsi 中添加代码 3.在msm8953-nopmi-qrd.dtsi中添加代码 二、在根文件系统中查看设备树 a. /sys/firmware/fdt b. /sys/firmware/devicetree c. /sys/devices/...

    目录

    一、修改设备树

        1.msm8953.dtsi 中添加code
        2. msm8953-pinctrl.dtsi 中添加代码
        3.在msm8953-nopmi-qrd.dtsi中添加代码

    二、在根文件系统中查看设备树

        a. /sys/firmware/fdt
        b. /sys/firmware/devicetree
        c. /sys/devices/platform
        d. /proc/device-tree

    三、问题
    四、查看修改驱动

    参考链接:MSM8937-MSM8953 UART配置调试指南

    uart驱动是使用内核驱动,无需自己编写,一般只需修改设备树。

    一、修改设备树

    设备树的配置有三部分:

    1.msm8953.dtsi 中添加code

    	blsp2_uart2: serial@7af0000 {
    		compatible = "qcom,msm-lsuart-v14";
    		reg = <0x7af0000 0x200>;
    		interrupts = <0 307 0>;
    		status = "disabled";
    		clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
    			<&clock_gcc clk_gcc_blsp2_ahb_clk>;
    		clock-names = "core_clk", "iface_clk";
    	};
    

    2. msm8953-pinctrl.dtsi 中添加代码

    		hsuart_active: default {
    			mux {
    				pins = "gpio20", "gpio21";
    				function = "blsp_uart6";
    			};
    
    			config {
    				pins = "gpio20", "gpio21";
    				drive-strength = <2>;
    				bias-disable;
    			};
    		};
    
    		hsuart_sleep: sleep {
    			mux {
    				pins = "gpio20", "gpio21";
    				function = "gpio";
    			};
    
    			config {
    				pins = "gpio20", "gpio21";
    				drive-strength = <2>;
    				bias-disable;
    			};
    		};
    

    3.在msm8953-nopmi-qrd.dtsi中添加代码 

    &blsp2_uart2 {
    	status = "ok";
    	pinctrl-names = "default";
    	pinctrl-0 = <&hsuart_active>;
    };
    

    设备树配置完成后,编译bootimage,刷机,重启。

    # user2 @ user2-HP-280-Pro-G2-MT-Legacy in ~/work/dujuan/out/target/product/msm8953_64 [14:13:25] 
    $ adb reboot bootloader       
    
    # user2 @ user2-HP-280-Pro-G2-MT-Legacy in ~/work/dujuan/out/target/product/msm8953_64 [14:13:30] 
    $ fastboot flash boot boot.img 
    target reported max download size of 536870912 bytes
    sending 'boot' (24775 KB)...
    OKAY [  0.710s]
    writing 'boot'...
    OKAY [  0.358s]
    finished. total time: 1.068s
    
    # user2 @ user2-HP-280-Pro-G2-MT-Legacy in ~/work/dujuan/out/target/product/msm8953_64 [14:13:35] 
    $ fastboot reboot
    

    设备启动后,却没有找到预期的/dev/ttyHSL3的设备节点。
    这里想到的是先确认设备树是否修改正确。

    二、在根文件系统中查看设备树

    参考资料:

    设备树学习(十、在根文件系统中查看设备树)
    在根文件系统中查看设备树(有助于调试)
    以下内核属于转载

    a. /sys/firmware/fdt

    进入/sys/firmware目录后便可看到二个文件,一个是devicetree文件夹,另一个是fdt(原始dtb文件,可以用hexdump -C fdt 将其打印出来查看就会发现里面的数据和dtb文件是一致的)。

    b. /sys/firmware/devicetree

    以目录结构呈现的dtb文件。 根节点对应base目录, 每一个节点对应一个目录, 每一个属性对应一个文件

    c. /sys/devices/platform

    系统中所有的platform_device, 有来自设备树的, 也有来有.c文件中注册的
    对于来自设备树的platform_device,可以进入 /sys/devices/platform/<设备名>/of_node 查看它的设备树属性(例如进入/sys/devices/platform/led/后若发现该目录下有of_node节点,就表明该platform_device来自设备树)

    d. /proc/device-tree

    是链接文件, 指向 /sys/firmware/devicetree/base

    查看dump的fdt文件,发现里面是有uart6的配置信息,且配置是正确的。
    然后到网络上寻找资料。

    三、问题 

    添加uart设备树配置后,在设备中没有找到对应的设备节点。
    

     四、查看修改驱动

    在网络找到参考资料中发现是需要修改驱动文件,在我这里的uart是配置的第4路uart,需要到kernel/msm-3.18/drivers/tty/serial路径下修改msm_serial_hs_lite.c文件。
    修改如下,添加一路uart

    static struct msm_hsl_port msm_hsl_uart_ports[] = {
    	{
    		.uart = {
    			.iotype = UPIO_MEM,
    			.ops = &msm_hsl_uart_pops,
    			.flags = UPF_BOOT_AUTOCONF,
    			.fifosize = 64,
    			.line = 0,
    		},
    	},
    	{
    		.uart = {
    			.iotype = UPIO_MEM,
    			.ops = &msm_hsl_uart_pops,
    			.flags = UPF_BOOT_AUTOCONF,
    			.fifosize = 64,
    			.line = 1,
    		},
    	},
    	{
    		.uart = {
    			.iotype = UPIO_MEM,
    			.ops = &msm_hsl_uart_pops,
    			.flags = UPF_BOOT_AUTOCONF,
    			.fifosize = 64,
    			.line = 2,
    		},
    	},
    	{
    		.uart = {
    			.iotype = UPIO_MEM,
    			.ops = &msm_hsl_uart_pops,
    			.flags = UPF_BOOT_AUTOCONF,
    			.fifosize = 64,
    			.line = 3,
    		},
    	},
    };
    

    查看log,有正确加载驱动会打印出detected port #%d (ttyHSL%d) 的log,分析probe函数。
    probe函数代码如下:

    static int msm_serial_hsl_probe(struct platform_device *pdev)
    {
    	struct msm_hsl_port *msm_hsl_port;
    	struct resource *uart_resource;
    	struct resource *gsbi_resource;
    	struct uart_port *port;
    	struct msm_serial_hslite_platform_data *pdata;
    	const struct of_device_id *match;
    	u32 line;
    	int ret;
    
    	if (pdev->id == -1)
    		pdev->id = atomic_inc_return(&msm_serial_hsl_next_id) - 1;
    
    	/* Use line (ttyHSLx) number from pdata or device tree if specified */
    	pdata = pdev->dev.platform_data;
    	if (pdata)
    		line = pdata->line;
    	else
    		line = pdev->id;
    
    	/* Use line number from device tree alias if present */
    	if (pdev->dev.of_node) {
    		dev_dbg(&pdev->dev, "device tree enabled\n");
    		ret = of_alias_get_id(pdev->dev.of_node, "serial");
    		if (ret >= 0)
    			line = ret;
    
    		pdata = msm_hsl_dt_to_pdata(pdev);
    		if (IS_ERR(pdata))
    			return PTR_ERR(pdata);
    
    		pdev->dev.platform_data = pdata;
    	}
    
    	if (unlikely(line < 0 || line >= UART_NR))	
    		return -ENXIO;
    
    	pr_info("detected port #%d (ttyHSL%d)\n", pdev->id, line);
    	......
    

    在probe函数代码中关于line的判断处理如下:

    // 这里 UART_NR的值是预处理的时候根据结构体msm_hsl_uart_ports元素个数确定的
    #define UART_NR	ARRAY_SIZE(msm_hsl_uart_ports)
    
    static int msm_serial_hsl_probe(struct platform_device *pdev)
    {
    
    	/* Use line (ttyHSLx) number from pdata or device tree if specified */
    	pdata = pdev->dev.platform_data;
    	if (pdata)
    		line = pdata->line;		// 这里有个疑问,这个pdata结构体中的line是谁来更新的?
    	else
    		line = pdev->id;
    
    	/* Use line number from device tree alias if present */
    	......
    
    	if (unlikely(line < 0 || line >= UART_NR))
    		return -ENXIO;	// 这里 UART_NR的值是预处理的时候就确定的
    

    综上:msm_hsl_uart_ports的元素个数是3的话,设备树中配置第四个uart会直接结束probe函数,不会打印相关log。
    在msm_hsl_uart_ports中添加一个元素即可解决我遇到的问题。 

     

     

     

     

    展开全文
  • 高通msm8909/msm8953 Linux支持双卡双待 高通msm8909/msm8953 Linux系统首次实现双卡双待功能: / # qlril-api-test QLRIL_Init success Copyright © 2020 Quectel, Smart Linux Group Name:QL RIL API, Supported...

    高通msm8909/msm8953 Linux支持双卡双待

    本文主要介绍QLRIL框架知识和API接口描述信息和使用方法。QLRIL接口支持通话、短信、网络、GNSS和AT命令查询等功能。
    在这里插入图片描述

    高通msm8909/msm8953 Linux系统首次实现双卡双待功能:
    / # qlril-api-test
    QLRIL_Init success
    Copyright © 2020 Quectel, Smart Linux
    Group Name:QL RIL API, Supported test cases:
    0: Help, Show all the API
    1: QLRIL_Init
    2: QLRIL_Exit
    3: QLRIL_GetVersion
    4: QLRIL_GetOperator
    5: QLRIL_GetCurrentCalls
    6: QLRIL_GetSimCardSlotId
    7: QLRIL_SetSimCardSlotId
    8: QLRIL_Dial
    9: QLRIL_SendSms
    10: QLRIL_SendSmsByPDU
    11: QLRIL_AcceptCall
    12: QLRIL_RejectCall
    13: QLRIL_SetupDataCall
    14: QLRIL_GetVoiceRegistrationState
    15: QLRIL_SetDataAllowed
    16: QLRIL_GetPreferredNetworkType
    17: QLRIL_SetPreferredNetworkType
    18: QLRIL_GetIccCardStatus
    19: QLRIL_SupplyIccPin
    20: QLRIL_SupplyIccPuk
    21: QLRIL_ChangeIccPin
    22: QLRIL_GetIMSI
    23: QLRIL_GetIMSIForApp
    24: QLRIL_GetDataCallList
    25: QLRIL_DeactivateDataCall
    26: QLRIL_SetRadioPower
    27: QLRIL_RequestShutdown
    28: QLRIL_GetVoiceRadioTechnology
    29: QLRIL_GetImsRegistrationState
    30: QLRIL_GetIMEI
    31: QLRIL_HangupConnection
    32: QLRIL_HangupWaitingOrBackground
    33: QLRIL_HangupForegroundResumeBackground
    34: QLRIL_GetMute
    35: QLRIL_SetMute
    36: QLRIL_GetSignalStrength
    37: QLRIL_SendAtCmd
    38: QLRIL_GetSIMPhoneNumber
    39: QLRIL_GetDeviceIdentity
    40: QLRIL_SetScreenState
    41: QLRIL_GetDataRegistrationState
    42: QLRIL_ResetQcrild
    50: QLRIL_RegisterEventsListener
    51: QLRIL_UnregisterEventsListener
    52: QLRIL_RegisterUnsolEvents
    53: QLRIL_UnregisterUnsolEvents
    54: QLRIL_GNSS_AddListener
    55: QLRIL_GNSS_DelListener
    56: QLRIL_GNSS_SetAttribute
    57: QLRIL_GNSS_RegisterEvents
    58: QLRIL_GNSS_UnregisterEvents
    59: QLRIL_GNSS_StartNavigation
    60: QLRIL_GNSS_StopNavigation
    61: QLRIL_GNSS_GetLocation
    62: Run the GNSS API test
    -1: Exit!

    Please input cmd index (-1: exit, 0: help):4
    ONS: CHN-UNICOM
    EONS: UNICOM
    MCCMNC: 46001

    Please input cmd index (-1: exit, 0: help):13
    Input an character: y - default; n - others;
    y
    setupDataCall response:
    status:0, retry:-1, callID:0, active:up
    type:IP, ifname:rmnet_data0, addresses:10.78.153.37/30, dnses:218.104.78.2 58.242.2.2
    gateways:10.78.153.38,pcscf:,mtu:1500

    QLRIL_SetupDataCall success

    Please input cmd index (-1: exit, 0: help):
    在这里插入图片描述
    在这里插入图片描述
    在这里插入图片描述

    展开全文
  • device_asus_msm8953-源码

    2021-03-27 13:00:01
    device_asus_msm8953
  • vendor_asus_msm8953-源码

    2021-03-27 03:37:48
    vendor_asus_msm8953
  • msm8953_xiaomi_alfak-源码

    2021-02-12 22:56:59
    msm8953_xiaomi_alfak
  • msm8953 lcd 驱动移植.pdf

    2021-01-15 15:46:28
    高通MSM8953平台LCM模组移植步骤,教程和多媒体指南截图。
  • msm8953 usb记录

    2019-12-31 11:44:05
    一、平台:msm8953 android 7.1.2 主要参考高通文档 设备树:kernel/msm-3.18/arch/arm/boot/dts/qcom/msm8953.dtsi usb3: ssusb@7000000{ compatible = "qcom,dwc-usb3-msm"; reg = <0x07000000 0xfc000>,...

    一、平台:msm8953 android 7.1.2 主要参考高通文档

    设备树:kernel/msm-3.18/arch/arm/boot/dts/qcom/msm8953.dtsi

    usb3: ssusb@7000000{
            compatible = "qcom,dwc-usb3-msm";
            reg = <0x07000000 0xfc000>,
                <0x0007e000 0x400>;
            reg-names = "core_base",
                "ahb2phy_base";
            #address-cells = <1>;
            #size-cells = <1>;
            ranges;

            interrupts = <0 136 0>, <0 220 0>, <0 134 0>;
            interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";

            USB3_GDSC-supply = <&gdsc_usb30>;
            qcom,usb-dbm = <&dbm_1p5>;
            qcom,msm-bus,name = "usb3";
            qcom,msm-bus,num-cases = <2>;
            qcom,msm-bus,num-paths = <1>;
            qcom,msm-bus,vectors-KBps =
                        <61 512 0 0>,
                        <61 512 240000 800000>;

            qcom,dwc-usb3-msm-tx-fifo-size = <21288>;

            clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
                <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>,
                <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
                <&clock_gcc clk_gcc_usb30_sleep_clk>,
                <&clock_gcc clk_xo_dwc3_clk>,
                <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;

            clock-names = "core_clk", "iface_clk", "utmi_clk",
                    "sleep_clk", "xo", "cfg_ahb_clk";

            dwc3@7000000 {
                compatible = "snps,dwc3";
                reg = <0x07000000 0xc8d0>;
                interrupt-parent = <&intc>;
                interrupts = <0 140 0>;
                usb-phy = <&qusb_phy>, <&ssphy>;
                tx-fifo-resize;
                snps,usb3-u1u2-disable;
                snps,nominal-elastic-buffer;
                snps,is-utmi-l1-suspend;
                snps,hird-threshold = /bits/ 8 <0x0>;
            };

    此处省略.......................

    };

     

    qcom,dwc-usb3-msm  对应kernel/msm-3.18/drivers/usb/dwc3/dwc3-msm.c

    snps,dwc3  对应 对应kernel/msm-3.18/drivers/usb/dwc3/core.c            //根节点

    二、初始化

    由于根节点与dwc3-msm驱动程序相对应,因此首先将其初始化。 该驱动程序的probe回调负责:
    1、初始化特定于驱动程序的资源
    工作队列– chg_work,id_work,resume_work等(特定于平台)

    2、初始化并启用USB内核所需的时钟
    Xo_clk,iface_clk,sleep_clk等(特定于平台)
    3、初始化regulators,HSPHY和SSPHY
    初始化和注册驱动程序特定的IRQ处理数的IRQ
    4、将设备注册到PM运行时层

    5、注册和设置公交车比例为SNOC
    6、读出DTSI参数和填充相应的变量
    DWC3 MSM驱动程序仅负责处理任何特定于MSM的设置和资源。

    三、中断

    The DWC3 MSM driver only has two interrupt handlers in the driver, which service:USB asynchronous interrupts –hs_phy_irq; RISING edge triggered

    PMIC ID interrupts –pmic_id_irq; DUAL edge triggered

    hs_phy_irq() is primarily used to wake up the controller when it is suspended after an HSPHY asynchronous interrupt occurs.

    The pmic_id_irq() handler is used to notify of the ID ground and ID float events, and propagatesthis to the DWC3 OTG driver

    四、HCD driver initialization

    dwc3_host_init() is responsible for setting up the necessary resources for the platform to run in
    host mode.
    dwc→xhci – Holds the platform_device allocated for the XHCI HCD. The dwc3_host_init()
    calls platform_device_add() that probes the respective XHCI HCD driver.
     Pdata.vendor – Carries the vendor ID
     Pdata.revision – Carries the DWC hardware revision
    dwc→xhci_resources – Has the I/O resources and controller base addresses when adding the
    platform device

    Adding the XHCI platform device
    For the XHCI controller driver to initialize correctly, it requires the minimum platform data fields
    to be set correctly. At least the resources must be added to the platform device structure, and the
    DWC3 XHCI-related parameters such as “vendor” and “revision” are optional, thus it is part of
    platform data.
    During the dwc3_probe() call, XHCI resources are populated with the IRQ resource along with
    the controller memory address and range. This is used later on when the platform device is added.

    五、DWC3 otg状态机介绍

    The OTG state machine is simplified to five states. The OTG states are:
    OTG_STATE_UNDEFINED – This state is only valid at first boot up. After the device
    moves to OTG_STATE_B_IDLE, this state is no longer valid.
    OTG_STATE_B_IDLE – This state is the default state of the OTG state machine. It has logic
    to handle both ID and BSV events.
    OTG_STATE_B_PERIPHERAL – This state occurs when the device acts in device mode.
    OTG_STATE_A_IDLE – This is a transition state into host mode after the USB ID is
    grounded. It attempts to start the host stack before continuing.
    OTG_STATE_A_HOST – This state occurs when the device acts in host mode.
    It also services the following state machine bits:
     B_SESS_VLD – B Session Valid
     ID – ID status

    六、otg状态机流程

    1. During bootup, the charger driver attains a reference to the USB power supply using
    power_supply_get_by_name().
    2. After the charger driver has a reference to the USB power supply, it can notify the USB
    driver of a VBUS event through qpnp_chg_usb_usbin_valid_irq_handler().
    3. The USBIN valid IRQ uses power_supply_set_present(), which has a registered callback of
    dwc3_msm_power_set_property_usb() in the USB driver.
    4. The USB driver sets mdwc→ext_xceiv.bsv to the value passed, which informs whether
    VBUS is high or low.
    5. dwc3_msm_power_set_property_usb() queues a delayed work to the resume_work work
    queue (delay = 20 ms).
    6. dwc3_resume_work() resumes the controller (if needed) using pm_runtime_get_sync() on
    mdwc→dev.
    7. The dwc3_resume_work() executes the hook to notify the DWC OTG driver of an external
    event (dwc3_ext_event_notify()).
    8. dwc3_ext_event_notify() handles setting/clearing the BSV state machine bit, and schedules
    work for the OTG state machine. (The event passed from resume_work is
    DWC3_EVENT_XCEIV_STATE.)
    9. dwc3_otg_sm_work() runs to service the BSV change (start/stop device stack).

    USB controller-based
    The USB controller-based VBUS detection mechanism is similar to the PMIC-based sequence.
    Only the detection is different and is handled within the DWC OTG driver. It does not involve
    any communication with the DWC MSM driver.
    The following process describes the USB controller-based sequence flow:
    1. The DWC3 controller has a separate interrupt line for handling ID/BSV events. The
    registered IRQ handlers for these events are dwc3_otg_interrupt().
    2. The dwc3_otg_interrupt() handler would be responsible for setting/clearing the BSV bit,
    which replaces dwc3_ext_event_notify() in the PMIC-based detection.
    3. After the correct state bits are set, the IRQ handler schedules for the
    dwc3_msm_otg_sm_work() to run. The next steps are identical to the PMCI-based sequence.

     

     

    展开全文
  • msm8953_linux_android_software_user_manual.pdf
  • 本文讲解了关于MSM8937 / MSM8953 MSM8940 / MSM8920 / MSM8917芯片组启动架构的概述
    说明:
    本文讲解了关于MSM8937 / MSM8953 MSM8940 / MSM8920 / MSM8917芯片组启动架构的概述
    处理器启动地址
    下面表格包括了MSM8937/MSM8953//MSM8940/MSM8920/MSM8917 芯片组包含的处理器. 处理器类型和启动地址.
    子系统/处理器 处理器 启动地址
    APPS
    Applications
    应用
    Cortex-A53 0x00100000*
    RPM
    Resource power Manager
    资源功耗管理
    Cortex-M3 0x00200000(子系统的视角) 0x0(系统的视角)
    Modem
    基带
    MSS_QDSP6 可配置的*
    WCNSS (Pronto) ARM9 0x0 or 0xFFFF0000 or 硬件重新映射*
    LPASS
    低功耗音频子系统
    (ADSP)
    LPASS_QDSP6 可配置的* LPASS  
    *系统和子系统视角中的引导地址没有变化
    启动调用堆栈
    TCM :Tightly-Coupled Memory,紧耦合内存
    Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory). This is usually just a few (4-64) KiB of RAM inside the ARM processor. 
    一些arm socs所谓的TCM(紧耦合的内存),通常是指ARM处理器内部的几个仅有(4 - 64)kb RAM
    CDT: Configuration Data Table,包含CDB0: platform info信息和CDB1: DDR配置参数。
    PIL:Peripheral image loader 外围设备镜像加载器
    HLOS: High-level operation system,高级操作系统,指包括Linux内核在内的整个Android系统
    组成 基于处理器 加载自 执行在 功能
    Application processor primary boot loader
    (APPS PBL)
    应用处理器PBL
    芯片内部代码
    Cortex-A53
    (AArch32)
    NA APPS ROM §启动设备和接口检测
    §紧急下载模式支持
    §加载并验证SBL1镜像片段在L2TCM和RPM code RAM
    Loads andauthenticates SBL1 ELF segments across L2TCMand RPM code RAM
    Secondary boot loader stage 1 (SBL1)
    二级引导加载程序阶段1
    sbl1.mbn
    Cortex-A53
    (AArch32)
    eMMC L2 TCM
    (分段1)
    L2 TCM 初始化内存子系统 (buses, DDR, clocks, and CDT)
    §加载/鉴定TrustZone, DEVCFG, RPM_FW, APPS BL 镜像(lk), memory dump 通过 USB 2.0 和 Sahara
    §看门狗调试保留, 比如, L2 刷新
    §RAM dump到eMMC/SD的支持, USB driver 的支持, USB 充电,温度检测, PMIC driver 的支持, 配置 DDR, and 刷新 L1/L2/ETB到崩溃调试
    §支持相关的配置
    OCIMEM(不懂) -
    RPM code RAM
    (分段2)
    RPM code RAM
    QSEE/TrustZone
    tz.mbn
    Cortex-A53
    (AArch64)
    eMMC LPDDR3 相当于 TZBSP
    §建立安全运行环境,
    §配置 xPU,
    §支持 fuse driver
    §验证一些子系统镜像
    §添加异常复位调试功能
    DEVCFG
    devcfg.mbn
    Cortex-A53
    (AArch64)
    eMMC LPDDR3 §OEM配置数据, 比如, xPU 配置
    §PIL 加载镜像区
    Debug policy1
    (不知道是什么)
    Cortex-A53
    (Aarch32)
    eMMC LPDDR3 商业安全设备上启用调试
    Resource Power Manager Firmware (RPM_FW)
    rpm.mbn
    Cortex-M3 eMMC RPM code RAM 资源功耗管理
    APPSBL/boot manager and OS loader
    emmc_appsboot.mbn
    Cortex-A532
    (AArch32/
    AArch64)
    eMMC LPDDR3 显示开机第一张图, 加载和验证kernel (实指linux kernel), and
    提供使用UEFI HLOS-specific引导加载程序的功能
    High-Level Operating System (HLOS)
    boot.img
    system.img
    userdata.img
    ...
    Cortex-A53
    (AArch32/AArch64)
    eMMC LPDDR3 Boots HLOS images, for example, A53 HLOS kernel image, WCNSS (Pronto) image, and so on.
    Modem Primary Boot Loader (Modem PBL)
    芯片内部代码
    MSS_QDSP6 NA Modem ROM
    Qualcomm® Hexagon™ TCM
    (data and stack)
    §创建 Hexagon TCM
    §从LPDDR3拷贝MBA到Hexagon TCM, 然后在Hexagon TCM中鉴定MBA
    Modem Boot Authenticator (MBA)
    NON-HLOS.bin
    MSS_QDSP6 eMMC Hexagon TCM §鉴定modem固件
    §xPU protects the DDR regions for modem, and memory dump
    1Debug policy固件是SBL可选择加载的固件. 更多信息参考Debug Policy Version 2 User Guide (80-NV396-72).
    2LK boot loader starts in 32-bit.

    启动流程
    1. 系统上电 ,让MSM8937/MSM8953/MSM8940/MSM8920应用处理器CPU复位.
    2. APPS PBL在Cortex-A53上运行, 加载并校验 SBL1
    a.SBL1 segment 1 from the boot device to L2 (as TCM).
    b.SBL1 segment 2 (SDI equivalent) to RPM code RAM, then jumps to SBL1.
    3. SBL1 segment 1 初始化DDR 并加载和校验以下内容:
    a.QSEE/TrustZone镜像从启动设备到DDR.
    b.DEVCFG镜像从启动设备到DDR.
    c.Debug Policy镜像从启动设备到DDR.
    d.HLOS APPSBL(lk)镜像从启动设备到DDR.
    e.RPM firmware镜像从启动设备到RPM code RAM.

    4. SBL1将执行权交给QSEE/TrustZone. QSEE/TrustZone建立安全环境, 配置 xPU, 支持the fuse driver.
    a.SBL1运行在32位模式. QSEE/TrustZoneruns运行在64位模式. 因为64位模式转变, SBL1 为QSEE入口设置加载重新映射, 写入RMR register,然后触发热启动. QSEE这时运行在64位模式.
    5. QSEE 通知RPM处理器来启动RPM固件执行.
    6. QSEE 将执行权限交给HLOS APPSBL(lk)来初始化系统.
    a.The Linux APPS boot loader (HLOS APPSBL) 一开始仅执行在32位模式下.
    b.这种做法是通过EL3/Monitor模式,通过查看ELF头对于HLOS APPSBL, 这表明它使用32位指令集架构. EL3/Monitor改变为32-bit模式并使得HLOS APPSBL执行在32-bit模式.
    7. HLOS APPSBL(lk)加载并校验HLOS kernel(Linux内核). LK通过在退出前使SCM调用安全监视器表明HLOS kernel64位模式. LK不像以前那样直接跳进内核.
    8. HLOS kernel加载MBA到DDR通过PIL.
    9. HLOS kernel带来Hexagon modem DSP重置.
    10. Modem PBL然后继续它的启动过程.
    11. HLOS kernel加载AMSS modem镜像到DDR通过PIL.
    12. Modem PBL校验MBA然后跳转到它.
    13. HLOS加载WCNSS (Pronto)镜像到DDR通过PIL.
    14. HLOS使WCNSS (Pronto)镜像重置,因此Pronto镜像开始执行.
    15. HLOS加载LPASS镜像到DDR通过PIL.
    16. HLOS使得LPASS镜像重置,LPASS镜像开始执行.

    注:本文大部分翻译自高通文档

    展开全文
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