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  • xdma

    2020-04-08 11:58:12
    xilinx xdma Linux 驱动 使用 xilinx 官网下载的linux xdma 驱动,在按照他们给的提示编译的时候会出现,一些问题 编译的时候,会出现证书的问题,官方说不用管, 插入内核的时候也会有一些错误。 int xdma_cdev_...

    xilinx xdma Linux 驱动 使用

    xilinx 官网下载的linux xdma 驱动,在按照他们给的提示编译的时候会出现,一些问题

    1. 编译的时候,会出现证书的问题,官方说不用管,
    2. 插入内核的时候也会有一些错误。

    会出现插入不了内核在这里插入图片描述

    int xdma_cdev_init(void)
    {
    	g_xdma_class = class_create(THIS_MODULE, XDMA_NODE_NAME);
    	if (IS_ERR(g_xdma_class)) {
    		dbg_init(XDMA_NODE_NAME ": failed to create class");
    		return -1;
    	}
    
        /* using kmem_cache_create to enable sequential cleanup */
        cdev_cache = kmem_cache_create("cdev_cache",
                                       sizeof(struct cdev_async_io),
                                       0,
                                       SLAB_HWCACHE_ALIGN,
                                       NULL);
        if (!cdev_cache) {
        	pr_info("memory allocation for cdev_cache failed. OOM\n");
        	return -ENOMEM;
        }
    
       	xdma_threads_create(8);
    
    	return 0;
    }
    

    修改

      	xdma_threads_create(4);
    

    还有脚本问题,会出现错误
    只能看他们的测试代码,然后在执行,
    由于电脑性能的原因,我把线程减少4个,然后再插入内核,能成功解决问题。

    展开全文
  • xdma driver

    2018-04-04 20:35:49
    xilinx xdma
  • xilinx xdma windows驱动

    2020-10-28 11:30:05
    This project is Xilinx's sample Windows driver for 'DMA/Bridge Subsystem for PCI Express' (XDMA) IP. This sample driver only has limited support for the XDMA IP features
  • 《基于XDMA的PCIE工程》参照https://blog.csdn.net/qq_40147893/article/details/118565988博客。
  • XDMA IP学习

    2021-07-15 19:27:58
    参考:xilinx xdma ipcore官方手册 PG195 一 XDMA IP概述 Xilinx® DMA/Bridge Subsystem for PCI Express® (PCIe®)(XDMA)是Xilinx公司2017年前后新推出的PCIe FPGA解决方案。功能上涵盖了PCIe ip核、SGDMA...

    参考:xilinx xdma ipcore官方手册 PG195


    一 XDMA IP概述

            Xilinx® DMA/Bridge Subsystem for PCI Express® (PCIe®)(XDMA)是Xilinx公司2017年前后新推出的PCIe FPGA解决方案。功能上涵盖了PCIe ip核、SGDMA功能、多通道分离,同时支持AXI总线访问等。

            XDMA支持UltraScale+、UltraScale和Virtex7 XT Gen3 (Endpoint),以及7系列(7A15T和7A25T除外)2.1(Endpoint)。最高支持4对Host-to-Card (H2C)和Card-to-Host (C2H)数据通道。

            XDMA IP能配置为两种模式。一种为DMA Data Mover,另一种为PCIe bridge,PCIe bridge只支持Ultra Scale+系列。一般用XDMA都是做DMA Data Mover模式,后面只整理DMA Data Mover模式的内容。

    二 XDMA IP结构

    2.1 PCIe ip核

            XDMA内部集成了PCIe的IP核,用于处理PCIe协议相关。PCIe core将PCIe接口组织为四个独立的AXIS的接口:

            PCIe Requester Request(RQ)接口,用户应用程序通过该接口生成对连接到该链路的远程PCIe设备的请求。

            PCIe Requester Completion(RC)接口,PCIe core将从链路接收的完成消息(响应于作为PCIe请求者的用户应用程序请求)返回给用户应用程序。

            PCIe Completer Request(CQ)接口,PCIe core将来自链路的请求传递到用户应用程序。

            PCIe Completer Completion(CC)接口,用户应用程序通过该接口将对CQ接口请求的响应发送回去。

    2.2通道接口

     2.2.1 DMA数据通道

            XDMA IP的DMA数据通道包含Host-to-Card (H2C)和Card-to-Host (C2H)两类,每类最高分别支持4通道。这些DMA通道可以被映射为独立AXI4-Stream接口或者是共享的AXI4-MM接口。(两者只能2选1):

            AXI Memory Mapped:AXI内存映射的接口,常见用于对接DDR、RAM等有地址寻址的外设。

            AXI Stream:AXI数据流接口,常用于对接FIFO等。

     2.2.2 寄存器通道

            The AXI4-Lite Master Configuration port:实现PCIE BAR地址到 AXI4-Lite寄存器地址的映射,可用来读写用户逻辑寄存器

            The AXI4-Lite Slave Configuration port:用户可通过此接口访问XDMA IP的PCIe集成模块的相关寄存器

            The AXI Memory Mapped Master CQ Bypass port: 用来实现PCIE 直通用户逻辑访问,可用于低延迟数据传输

    注:AXI4-Lite Master Configuration port这个接口的数据输出是经过XDMA内部过滤的,也就是说这个接口出来的地址并不是所有的都能给用户使用,有部分地址是用来对XDMA的寄存器配置使用的,容易造成用户地址和配置地址混合,使用时需要注意。如果是对用户侧寄存器的大量访问最好使用The AXI Memory Mapped Master CQ Bypass port。

    2.3 DMA

            XDMA采用SGDMA。采用了一系列的descriptors,这些descriptors组成了一个链接列表。它们用来指明DMA transfers的源地址、目的地址以及DMA transfer的长度。他们由驱动程序产生。并且存储在host 内存中。DMA中的控制器会发起抓取descriptor lists来完成初始化并开始执行DMA操作。描述符的结构如下:

            每个DMA通道都会有自己的descriptors列表。DMA读取到一个descriptor之后会提取其中Src_addr与Dst_addr,然后根据这些地址来完成memory transfer。完成当前descriptor对应的transfer之后。DMA 通道会根据当前descriptor的Nxt_addr来抓取下一个descriptor。而且descriptor中的Nxt_adj记录了列表中还剩下未完成的descriptor的个数。一旦为0,那么当前descriptor的control字段中的STOP位会置高。DMA就会停止抓取descriptor。

     

           C2H和H2C的DMA传输流程如下图所示,其中绿色为应用层,橙色为驱动层,蓝色为硬件。

     

     2.3中断

            XDMA的IRQ模块能接受用户的外部中断和DMA通道的内部中断进而通过PCIe向链路产生中断。XDMA支持MSI-X,MSI和Legacy Interrupts(传统中断)。注:Host能使能一种或多种中断类型,当多个中断使能时,IP在一定时间内只能产生一种中断,其中MSI-X中断的优先级高于MSI,MSI优先级高于Legacy Interrupts,当一个类型中断产生或者挂起时,软件无法进行类型切换。下面分别介绍三种类型的中断:

    (1)Legacy Interrupts

            对于Legacy Interrupts中断,当user_irq_ack 第一次为1的时候,代表中断已经被PCIe发送,之后才可以将usr_irq_req清0,当user_irq_ack 第二次为1的时候,可以重新设置usr_irq_req发起中断。

    (2)MSI和MSI-X

            MSI中断和MSI-X都是往配置的CPU中断寄存器里进行memory写操作,来产生中断,效率比INTx是共享式高,其中MSI最多支持32个中断向量,而且要求中断向量连续;而MSI-X中断机制可以支持更多的中断请求,而且不要求中断向量连续。

            usr_irq_req 置位之后要一直保持到user_irq_ack置位且中断被Host处理。user_irq_ack 为置位只是说明中断已经被主机接收了,但是不代表已经处理。可以通过延迟usr_irq_req足够长的时间,确保中断能被响应,或者通过软件或者驱动层去清零usr_irq_req,比如通过AXI-LITE接口下发命令清除usr_irq_req。

    注:当MSI和MSI-X同时使能时,产生为MSI-X

    注2:关于XDMA的MSI-X的usr_irq_reg的清楚时机,xdma手册上不同版本描述不同,V4.1与V3.1与本文相同,V4.0中认为usr_irq_ack置位之后就可以清除usr_irq_reg。此块待验证。

     2.4 寄存器空间

    2.4.1 BAR

            是否使能The AXI4-Lite Master Configuration portThe AXI Memory Mapped Master CQ Bypass port会导致不同的BARs分配。如下表:

    2.4.2 BAR对应的寄存器 

             参考PG195

    三 XDMA IP核配置

            本次使用xilinx官方开发板KCU116(FPGA为KU5P)做相关实验,生成AXI-MM官方例程,对应IP核配置如下。 

    3.1 Basic

            Functional mode:功能模式,选择DMA模式。

            Mode:配置模式,选择Advanced高级配置。

            Lane Width:根据硬件选择X8

            Max Link Speed: 选择 8.0GT/s 即GEN3

            Reference Clock:例程使用PCIe插槽传过来参考时钟,100MHz。

            GT Quad:根据硬件选择GTY Quad 225(硬件上x8占用了Quad 224和225,选择PCIe Lan0的Quad 225)

            DMA Interface Option:接口选择AXI-MM

            AXI Data Width:选择默认256bit

            AXI Clock Frequency:选择默认250M

            AXI-Lite Slave Interface:用于选通AXI4-Lite Slave Configuration port通道。

    3.2 PCIe ID

             板子只有一个PCIe,这页选择默认配置

    3.3 PCIe BARs

             PCIE to AXI Lite Master Interface:这个接口的数据输出是经过XDMA内部过滤的,接口出来的地址并不是所有的都能给用户使用,有部分地址是用来对XDMA的寄存器配置使用的,使用时注意区分开。使用AXI-Lite接口

            PCIE to DMA Bypass Interface:这个接口不经过DMA直接访问用户逻辑,使用AXI-MM接口

            PCIE to AXI Translation: 这个设置比较重要,通常情况下,主机侧PCIE BAR地址与用户逻辑侧地址是不一样的,这个设置就是进行BAR地址到AXI地址的转换,比如主机一侧BAR地址为0,IP里面转换设置为0x80000000,则主机访问BAR地址0转换到AXI Lite 总线地址就是0x80000000

    3.4 PCIe MISC

            选择对应的中断请求数,中断类型以及对应的中断向量数。通常linux只支持一个MSI的中断向量。

     3.5 PCIe DMA

            设置所需的Number of DMA Read Channel(H2C)和Number of DMA Write Channel(C2H)

            Number of Request IDs for Read(Write)channel :这个是每个通道设置允许最大的outstanding数量,按照默认即可。

    展开全文
  • PCIE_XDMA测试

    千次阅读 2020-02-26 17:28:53
  • Xilinx xdma Linux平台使用

    千次阅读 2019-05-06 20:41:41
    下载Xilinx_Answer_65444_Linux_Files_rel20180420.zip,修改xdma/libxdma.c,添加, #include <linux/slab.h> /*add by zc*/ 编译, $ cd xdma $ make 测试, xdma:xdma_mod_init: desc_blen_max: ...

    作者

    QQ群:852283276
    微信:arm80x86
    微信公众号:青儿创客基地
    B站:主页 https://space.bilibili.com/208826118

    方法

    官网下载驱动,我下载2017.4版本的,当时还有18.2版本,由于vivado是17.4,实测发现windows下,18.2版本的驱动无法操作17.4的FPGA,切换到老版本即可。ubuntu 16.04.4编译17.4驱动需要修改代码,

    #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)
    		dbg_init("Enabling MSI-X\n");
    		rc = pci_alloc_irq_vectors(pdev, req_nvec, req_nvec,
    					PCI_IRQ_MSIX);
    #else
    		int i;
    
    		dbg_init("Enabling MSI-X\n");
    		for (i = 0; i < req_nvec; i++)
    			xdev->entry[i].entry = i;
    
    		rc = pci_enable_msix(pdev, xdev->entry, req_nvec);
    #endif
    

    测试,PCIe2.0x4,带宽位1.5GB/s,达到满速状态,

    jj@jj-pc:~/xdma/tests$ sudo ./dma_to_device -d /dev/xdma0_h2c_0 -a 0 -s 0x400000 -c 16 -v
    sscanf() = 1, value = 0x00000000
    sscanf() = 1, value = 0x00400000
    sscanf() = 1, value = 0x00000010
    device = /dev/xdma0_h2c_0, address = 0x00000000, size = 0x00400000, offset = 0x00000000, count = 16
    host memory buffer = 0x7f03545a4000
    CLOCK_MONOTONIC reports 0.002827977 seconds (total) for last transfer of 4194304 bytes
    jj@jj-pc:~/xdma/tests$ sudo ./dma_from_device -d /dev/xdma0_c2h_0 -a 0 -s 0x400000 -c 16 -v
    sscanf() = 1, value = 0x00000000
    sscanf() = 1, value = 0x00400000
    sscanf() = 1, value = 0x00000010
    device = /dev/xdma0_c2h_0, address = 0x00000000, size = 0x00400000, offset = 0x00000000, count = 16
    host memory buffer = 0x7f8b21ff7000
    CLOCK_MONOTONIC reports 0.003003013 seconds (total) for last transfer of 4194304 bytes
    

    Linux

    下载Xilinx_Answer_65444_Linux_Files_rel20180420.zip,修改xdma/libxdma.c,添加,

    #include <linux/slab.h> /*add by zc*/
    

    编译,

    $ cd xdma
    $ make
    

    测试,

    xdma:xdma_mod_init: desc_blen_max: 0xfffffff/268435455, sgdma_timeout: 10 sec.
    xdma:xdma_device_open: xdma device 0000:07:00.0, 0xc00000007e309000.
    xdma:map_single_bar: BAR0 at 0xc44000000 mapped at 0x8000080090ac0000, length=65536(/65536)
    xdma:map_bars: config bar 0, pos 0.
    xdma:identify_bars: 1 BARs: config 0, user -1, bypass -1.
    xdma:check_nonzero_interrupt_status: 0000:07:00.0 xdma0 user_int_pending = 0x00000001
    xdma:probe_one: 0000:07:00.0 xdma0, pdev 0xc00000007e309000, xdev 0xc00000007c2de000, 0xc00000007e278000, usr 16, ch 1,1.
    

    x86

    2017.4版本,打开调试,开机打印,

    jj@jj-pc:~/x86-static-16.04.4/bin$ dmesg -c
    [  181.916322] xdma v2017.0.45
    [  181.916323] xdma_init():xdma init()
    [  181.916353] probe():probe(pdev = 0xffff934e1a6dd000, pci_id = 0xffffffffc08a03c0)
    [  181.916354] alloc_dev_instance():probe() lro = 0xffff934e18918000
    [  181.916426] probe():pci_set_master()
    [  181.916435] probe_scan_for_msi():pci_enable_msi()
    [  181.916462] request_regions():pci_request_regions()
    [  181.916467] map_single_bar():BAR0: 65536 bytes to be mapped.
    [  181.916491] map_single_bar():BAR0 at 0xf7d00000 mapped at 0xffffa2fbc1780000, length=65536(/65536)
    [  181.916494] is_config_bar():BAR 0 is the XDMA config BAR
    [  181.916495] map_single_bar():BAR #1 is not present - skipping
    [  181.916496] map_single_bar():BAR #2 is not present - skipping
    [  181.916497] map_single_bar():BAR #3 is not present - skipping
    [  181.916498] map_single_bar():BAR #4 is not present - skipping
    [  181.916498] map_single_bar():BAR #5 is not present - skipping
    [  181.916500] set_dma_mask():sizeof(dma_addr_t) == 8
    [  181.916501] set_dma_mask():Could not set 64-bit DMA mask.
    [  181.916502] set_dma_mask():Using a 32-bit DMA mask.
    [  181.916514] irq_setup():Using IRQ#30 with 0xffff934e18918000
    [  181.916516] probe_for_engine():Probing for H2C 0 engine at ffffa2fbc1780000
    [  181.916519] probe_for_engine():engine ID = 0x1fc0
    [  181.916519] probe_for_engine():engine channel ID = 0x0
    [  181.916521] probe_for_engine():Found H2C 0 AXI engine at ffffa2fbc1780000
    [  181.916523] engine_create():engine ffff934d335aca00 name H2C irq_bitmask=0x00000001
    [  181.916525] engine_alignments():engine ffff934d335aca00 name H2C alignments=0x00010140
    [  181.916526] engine_alignments():align_bytes = 1
    [  181.916527] engine_alignments():granularity_bytes = 1
    [  181.916527] engine_alignments():address_bits = 64
    [  181.916529] probe_for_engine():Probing for H2C 1 engine at ffffa2fbc1780100
    [  181.916531] probe_for_engine():engine ID = 0x0
    [  181.916532] probe_for_engine():engine channel ID = 0x0
    [  181.916533] probe_for_engine():Incorrect engine ID - skipping
    [  181.916534] probe_for_engine():Probing for H2C 2 engine at ffffa2fbc1780200
    [  181.916536] probe_for_engine():engine ID = 0x0
    [  181.916537] probe_for_engine():engine channel ID = 0x0
    [  181.916538] probe_for_engine():Incorrect engine ID - skipping
    [  181.916538] probe_for_engine():Probing for H2C 3 engine at ffffa2fbc1780300
    [  181.916541] probe_for_engine():engine ID = 0x0
    [  181.916542] probe_for_engine():engine channel ID = 0x0
    [  181.916542] probe_for_engine():Incorrect engine ID - skipping
    [  181.916543] probe_for_engine():Probing for C2C 0 engine at ffffa2fbc1781000
    [  181.916546] probe_for_engine():engine ID = 0x1fc1
    [  181.916547] probe_for_engine():engine channel ID = 0x0
    [  181.916548] probe_for_engine():Found C2H 0 AXI engine at ffffa2fbc1781000
    [  181.916550] engine_create():engine ffff934d335ace00 name C2H irq_bitmask=0x00000002
    [  181.916552] engine_alignments():engine ffff934d335ace00 name C2H alignments=0x00010140
    [  181.916552] engine_alignments():align_bytes = 1
    [  181.916553] engine_alignments():granularity_bytes = 1
    [  181.916554] engine_alignments():address_bits = 64
    [  181.916555] probe_for_engine():Probing for C2C 1 engine at ffffa2fbc1781100
    [  181.916557] probe_for_engine():engine ID = 0x0
    [  181.916558] probe_for_engine():engine channel ID = 0x0
    [  181.916559] probe_for_engine():Incorrect engine ID - skipping
    [  181.916560] probe_for_engine():Probing for C2C 2 engine at ffffa2fbc1781200
    [  181.916562] probe_for_engine():engine ID = 0x0
    [  181.916563] probe_for_engine():engine channel ID = 0x0
    [  181.916564] probe_for_engine():Incorrect engine ID - skipping
    [  181.916565] probe_for_engine():Probing for C2C 3 engine at ffffa2fbc1781300
    [  181.916567] probe_for_engine():engine ID = 0x0
    [  181.916568] probe_for_engine():engine channel ID = 0x0
    [  181.916569] probe_for_engine():Incorrect engine ID - skipping
    [  181.916570] create_interfaces():No user logic BAR detected - skip device setup
    [  181.916571] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.916573] gen_dev_major():Dynamic allocated major=244, rc=0
    [  181.917746] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.917954] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918502] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918537] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918559] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918582] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918604] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918627] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918650] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918811] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918840] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918862] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918885] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918905] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.918945] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.919522] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0x          (null))
    [  181.919557] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0xffff934d335aca00)
    [  181.919581] create_sg_char():xdma(lro = 0xffff934e18918000, engine = 0xffff934d335ace00)
    [  181.919604] create_interfaces():No bypass BAR detected - skip device setup
    [  181.919607] read_interrupts():ioread32(0xffffa2fbc1782040) returned 0x00000000 (user_int_request).
    [  181.919608] read_interrupts():ioread32(0xffffa2fbc1782044) returned 0x00000000 (channel_int_request)
    [  181.919609] Create device attribute file for major =244, instance = 0
    [  181.919611] Device file created successfully
    

    发送数据到板卡,板卡读,

    jj@jj-pc:~/x86-static-16.04.4/bin$ sudo ./dma_to_device -d /dev/xdma0_h2c_0 -a 0x1000000000 -s 4096 -v
    sscanf() = 1, value = 0x00001000
    device = /dev/xdma0_h2c_0, address = 0x1000000000, size = 0x00001000, offset = 0x00000000, count = 1
    host memory buffer = 0xeaf000
    CLOCK_MONOTONIC reports 0.000169817 seconds (total) for last transfer of 4096 bytes
    jj@jj-pc:~/x86-static-16.04.4/bin$ dmesg -c
    [  250.317286] char_sgdma_open(): H2C0: char_sgdma_open(0xffff934e14becb68, 0xffff934dbdca5b00)
    [  250.317290] char_sgdma_llseek():char_sgdma_llseek: pos=68719476736
    [  250.317299] char_sgdma_read_write(): H2C0: seq:0 file=0xffff934dbdca5b00, buf=0x0000000000eaf000, count=4096, pos=68719476736
    [  250.317301] char_sgdma_read_write(): H2C0: seq:0 dir_to_dev=1 write request
    [  250.317302] char_sgdma_read_write(): H2C0: H2C engine channel 0 (engine num 0)= 0xffff934d335aca00
    [  250.317303] char_sgdma_read_write(): H2C0: lro = 0xffff934e18918000
    [  250.317305] char_sgdma_read_write(): H2C0: res = 0, remaining = 4096
    [  250.317306] transfer_create():transfer_create()
    [  250.317309] transfer_create():mapped_pages=1.
    [  250.317310] transfer_create():sgl = 0xffff934dd3025180.
    [  250.317313] transfer_create():hwnents=1.
    [  250.317314] transfer_create():sg_page(&sgl[0])=0xffffc9c0c445b640.
    [  250.317315] transfer_create():sg_dma_address(&sgl[0])=0x00000000d46b2000.
    [  250.317316] transfer_create():sg_dma_len(&sgl[0])=0x00001000.
    [  250.317318] transfer_create():transfer_create():
    [  250.317319] transfer_create():transfer->desc_bus = 0xbdc59000.
    [  250.317320] transfer_build():SGLE    0: addr=0x00000000d46b2000 length=0x00001000
    [  250.317322] transfer_build():DESC    0: cont_addr=0xd46b2000 cont_len=0x00001000 ep_addr=0x1000000000
    [  250.317323] transfer_create():transfer 0xffff934e14c2ca00 has 1 descriptors
    [  250.317324] transfer_data(): H2C0: seq:0 transfer=0xffff934e14c2ca00.
    [  250.317325] transfer_dump():Descriptor Entry (Pre-Transfer)
    [  250.317327] dump_desc():0xffff934dbdc59000/0x00: 0xad4b0013 0xad4b0013 magic|extra_adjacent|control
    [  250.317328] dump_desc():0xffff934dbdc59004/0x04: 0x00001000 0x00001000 bytes
    [  250.317330] dump_desc():0xffff934dbdc59008/0x08: 0xd46b2000 0xd46b2000 src_addr_lo
    [  250.317331] dump_desc():0xffff934dbdc5900c/0x0c: 0x00000000 0x00000000 src_addr_hi
    [  250.317332] dump_desc():0xffff934dbdc59010/0x00: 0x00000000 0x00000000 dst_addr_lo
    [  250.317334] dump_desc():0xffff934dbdc59014/0x04: 0x00000010 0x00000010 dst_addr_hi
    [  250.317335] dump_desc():0xffff934dbdc59018/0x08: 0x00000000 0x00000000 next_addr
    [  250.317336] dump_desc():0xffff934dbdc5901c/0x0c: 0x00000000 0x00000000 next_addr_pad
    [  250.317337] dump_desc():
    [  250.317339] transfer_queue(): H2C0: transfer_queue(transfer=0xffff934e14c2ca00).
    [  250.317340] transfer_queue(): H2C0: transfer_queue(): starting H2C engine.
    [  250.317341] engine_start(): H2C0: engine_start(H2C): transfer=0xffff934e14c2ca00.
    [  250.317342] engine_start(): H2C0: iowrite32(0xbdc59000 to 0xffffa2fbc1784080) (first_desc_lo)
    [  250.317344] engine_start(): H2C0: iowrite32(0x00000000 to 0xffffa2fbc1784084) (first_desc_hi)
    [  250.317345] engine_start(): H2C0: iowrite32(0x00000000 to 0xffffa2fbc1784088) (first_desc_adjacent)
    [  250.317346] engine_start(): H2C0: ioread32(0xffffa2fbc1780040) (dummy read flushes writes).
    [  250.317347] engine_start_mode_config(): H2C0: iowrite32(0x00f83e1f to 0xffffa2fbc1780004) (control)
    [  250.317350] engine_start_mode_config(): H2C0: ioread32(0xffffa2fbc1780040) = 0x00000001 (dummy read flushes writes).
    [  250.317351] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780000).
    [  250.317353] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780000) returned 0x1fc00006.
    [  250.317363] xdma_isr():(irq=30) <<<< INTERRUPT SERVICE ROUTINE
    [  250.317365] xdma_isr():ch_irq = 0x00000001
    [  250.317366] xdma_isr():user_irq = 0x00000000
    [  250.317367] xdma_isr(): H2C0: schedule_work(engine=ffff934d335aca00)
    [  250.317373] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780040) returned 0x00000006 (status).
    [  250.317375] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780004) returned 0x00f83e1f (control)
    [  250.317377] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784080) returned 0xbdc59000 (first_desc_lo)
    [  250.317378] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784084) returned 0x00000000 (first_desc_hi)
    [  250.317380] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784088) returned 0x00000000 (first_desc_adjacent).
    [  250.317382] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780048) returned 0x00000001 (completed_desc_count).
    [  250.317384] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780090) returned 0x00f83e1e (interrupt_enable_mask)
    [  250.317385] engine_status_read(): H2C0: Status of SG DMA H2C engine:
    [  250.317386] engine_status_read(): H2C0: ioread32(0xffffa2fbc1780040).
    [  250.317389] engine_status_read(): H2C0: status = 0x00000006: IDLE DESC_STOPPED DESC_COMPLETED 
    [  250.317390] engine_start(): H2C0: H2C engine 0xffff934d335aca00 now running
    [  250.317391] transfer_queue(): H2C0: transfer=0xffff934e14c2ca00 started H2C engine with transfer 0xffff934e14c2ca00.
    [  250.317392] transfer_queue(): H2C0: engine->running = 1
    [  250.317396] engine_service_work(): H2C0: engine_service() for H2C engine ffff934d335aca00
    [  250.317398] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780000).
    [  250.317399] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780000) returned 0x1fc00006.
    [  250.317401] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780040) returned 0x00000006 (status).
    [  250.317403] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780004) returned 0x00f83e1f (control)
    [  250.317405] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784080) returned 0xbdc59000 (first_desc_lo)
    [  250.317407] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784084) returned 0x00000000 (first_desc_hi)
    [  250.317409] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1784088) returned 0x00000000 (first_desc_adjacent).
    [  250.317411] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780048) returned 0x00000001 (completed_desc_count).
    [  250.317413] engine_reg_dump(): H2C0: ioread32(0xffffa2fbc1780090) returned 0x00f83e1e (interrupt_enable_mask)
    [  250.317414] engine_status_read(): H2C0: Status of SG DMA H2C engine:
    [  250.317415] engine_status_read(): H2C0: ioread32(0xffffa2fbc1780040).
    [  250.317417] engine_status_read(): H2C0: status = 0x00000006: IDLE DESC_STOPPED DESC_COMPLETED 
    [  250.317418] engine_service_shutdown(): H2C0: engine just went idle, resetting RUN_STOP.
    [  250.317419] xdma_engine_stop(): H2C0: xdma_engine_stop(engine=ffff934d335aca00)
    [  250.317421] xdma_engine_stop(): H2C0: Stopping SG DMA H2C engine; writing 0x00f83e1e to 0xffffa2fbc1780004.
    [  250.317422] xdma_engine_stop(): H2C0: xdma_engine_stop(H2C) done
    [  250.317423] engine_service(): H2C0: desc_count = 1
    [  250.317425] engine_service(): H2C0: head of queue transfer 0xffff934e14c2ca00 has 1 descriptors
    [  250.317426] engine_service(): H2C0: Engine completed 1 desc, 1 not yet dequeued
    [  250.317428] engine_service_final_transfer(): H2C0: engine H2C completed transfer
    [  250.317429] engine_service_final_transfer(): H2C0: Completed transfer ID = 0xffff934e14c2ca00
    [  250.317430] engine_service_final_transfer(): H2C0: *pdesc_completed=1, transfer->desc_num=1
    [  250.317432] engine_service_resume(): H2C0: no pending transfers, H2C engine stays idle.
    [  250.317447] transfer_data(): H2C0: transfer ffff934e14c2ca00 completed
    [  250.317451] transfer_data(): H2C0: remain=0, done=4096
    [  250.317453] char_sgdma_read_write(): H2C0: seq:0 char_sgdma_read_write() return=4096.
    [  250.317454] interrupt_status():reg = ffffa2fbc1782000
    [  250.317455] interrupt_status():&reg->user_int_enable = ffffa2fbc1782004
    [  250.317457] interrupt_status():user_int_enable = 0x00000001
    [  250.317458] interrupt_status():channel_int_enable = 0x00000003
    [  250.317460] interrupt_status():user_int_request = 0x00000000
    [  250.317462] interrupt_status():channel_int_request = 0x00000000
    [  250.317463] interrupt_status():user_int_pending = 0x00000000
    [  250.317465] interrupt_status():channel_int_pending = 0x00000000
    [  250.317481] char_sgdma_close(): H2C0: char_sgdma_close(0xffff934e14becb68, 0xffff934dbdca5b00)
    

    接收数据,板卡写,

    jj@jj-pc:~/x86-static-16.04.4/bin$ sudo ./dma_from_device -d /dev/xdma0_c2h_0 -a 0x1000000000 -s 4096 -v
    sscanf() = 1, value = 0x00001000
    device = /dev/xdma0_c2h_0, address = 0x1000000000, size = 0x00001000, offset = 0x00000000, count = 1
    host memory buffer = 0x12d9000
    CLOCK_MONOTONIC reports 0.000137324 seconds (total) for last transfer of 4096 bytes
    jj@jj-pc:~/x86-static-16.04.4/bin$ dmesg -c
    [  333.802040] char_sgdma_open(): C2H0: char_sgdma_open(0xffff934e14bee428, 0xffff934e146e3b00)
    [  333.802046] char_sgdma_llseek():char_sgdma_llseek: pos=68719476736
    [  333.802055] char_sgdma_read_write(): C2H0: seq:1 file=0xffff934e146e3b00, buf=0x00000000012d9000, count=4096, pos=68719476736
    [  333.802057] char_sgdma_read_write(): C2H0: seq:1 dir_to_dev=0 read request
    [  333.802058] char_sgdma_read_write(): C2H0: C2H engine channel 0 (engine num 1)= 0xffff934d335ace00
    [  333.802059] char_sgdma_read_write(): C2H0: lro = 0xffff934e18918000
    [  333.802060] char_sgdma_read_write(): C2H0: res = 0, remaining = 4096
    [  333.802062] transfer_create():transfer_create()
    [  333.802064] transfer_create():mapped_pages=1.
    [  333.802065] transfer_create():sgl = 0xffff934d34c71060.
    [  333.802066] transfer_create():hwnents=1.
    [  333.802067] transfer_create():sg_page(&sgl[0])=0xffffc9c0c2c563c0.
    [  333.802068] transfer_create():sg_dma_address(&sgl[0])=0x00000000b158f000.
    [  333.802069] transfer_create():sg_dma_len(&sgl[0])=0x00001000.
    [  333.802071] transfer_create():transfer_create():
    [  333.802071] transfer_create():transfer->desc_bus = 0xc0bfd000.
    [  333.802073] transfer_build():SGLE    0: addr=0x00000000b158f000 length=0x00001000
    [  333.802074] transfer_build():DESC    0: cont_addr=0xb158f000 cont_len=0x00001000 ep_addr=0x1000000000
    [  333.802075] transfer_create():transfer 0xffff934e14c2cb00 has 1 descriptors
    [  333.802077] transfer_data(): C2H0: seq:1 transfer=0xffff934e14c2cb00.
    [  333.802078] transfer_dump():Descriptor Entry (Pre-Transfer)
    [  333.802079] dump_desc():0xffff934dc0bfd000/0x00: 0xad4b0013 0xad4b0013 magic|extra_adjacent|control
    [  333.802081] dump_desc():0xffff934dc0bfd004/0x04: 0x00001000 0x00001000 bytes
    [  333.802082] dump_desc():0xffff934dc0bfd008/0x08: 0x00000000 0x00000000 src_addr_lo
    [  333.802083] dump_desc():0xffff934dc0bfd00c/0x0c: 0x00000010 0x00000010 src_addr_hi
    [  333.802085] dump_desc():0xffff934dc0bfd010/0x00: 0xb158f000 0xb158f000 dst_addr_lo
    [  333.802086] dump_desc():0xffff934dc0bfd014/0x04: 0x00000000 0x00000000 dst_addr_hi
    [  333.802087] dump_desc():0xffff934dc0bfd018/0x08: 0x00000000 0x00000000 next_addr
    [  333.802089] dump_desc():0xffff934dc0bfd01c/0x0c: 0x00000000 0x00000000 next_addr_pad
    [  333.802089] dump_desc():
    [  333.802091] transfer_queue(): C2H0: transfer_queue(transfer=0xffff934e14c2cb00).
    [  333.802092] transfer_queue(): C2H0: transfer_queue(): starting C2H engine.
    [  333.802093] engine_start(): C2H0: engine_start(C2H): transfer=0xffff934e14c2cb00.
    [  333.802095] engine_start(): C2H0: iowrite32(0xc0bfd000 to 0xffffa2fbc1785080) (first_desc_lo)
    [  333.802096] engine_start(): C2H0: iowrite32(0x00000000 to 0xffffa2fbc1785084) (first_desc_hi)
    [  333.802097] engine_start(): C2H0: iowrite32(0x00000000 to 0xffffa2fbc1785088) (first_desc_adjacent)
    [  333.802098] engine_start(): C2H0: ioread32(0xffffa2fbc1781040) (dummy read flushes writes).
    [  333.802100] engine_start_mode_config(): C2H0: iowrite32(0x00f83e1f to 0xffffa2fbc1781004) (control)
    [  333.802102] engine_start_mode_config(): C2H0: ioread32(0xffffa2fbc1781040) = 0x00000001 (dummy read flushes writes).
    [  333.802103] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781000).
    [  333.802105] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781000) returned 0x1fc10006.
    [  333.802107] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781040) returned 0x00000006 (status).
    [  333.802109] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781004) returned 0x00f83e1f (control)
    [  333.802111] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785080) returned 0xc0bfd000 (first_desc_lo)
    [  333.802113] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785084) returned 0x00000000 (first_desc_hi)
    [  333.802114] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785088) returned 0x00000000 (first_desc_adjacent).
    [  333.802116] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781048) returned 0x00000001 (completed_desc_count).
    [  333.802118] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781090) returned 0x00f83e1e (interrupt_enable_mask)
    [  333.802119] xdma_isr():(irq=30) <<<< INTERRUPT SERVICE ROUTINE
    [  333.802121] xdma_isr():ch_irq = 0x00000002
    [  333.802123] engine_status_read(): C2H0: Status of SG DMA C2H engine:
    [  333.802124] engine_status_read(): C2H0: ioread32(0xffffa2fbc1781040).
    [  333.802126] engine_status_read(): C2H0: status = 0x00000006: IDLE DESC_STOPPED DESC_COMPLETED 
    [  333.802126] xdma_isr():user_irq = 0x00000000
    [  333.802128] xdma_isr(): C2H0: schedule_work(engine=ffff934d335ace00)
    [  333.802130] engine_start(): C2H0: C2H engine 0xffff934d335ace00 now running
    [  333.802131] transfer_queue(): C2H0: transfer=0xffff934e14c2cb00 started C2H engine with transfer 0xffff934e14c2cb00.
    [  333.802132] transfer_queue(): C2H0: engine->running = 1
    [  333.802134] engine_service_work(): C2H0: engine_service() for C2H engine ffff934d335ace00
    [  333.802135] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781000).
    [  333.802137] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781000) returned 0x1fc10006.
    [  333.802139] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781040) returned 0x00000006 (status).
    [  333.802141] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781004) returned 0x00f83e1f (control)
    [  333.802143] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785080) returned 0xc0bfd000 (first_desc_lo)
    [  333.802145] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785084) returned 0x00000000 (first_desc_hi)
    [  333.802147] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1785088) returned 0x00000000 (first_desc_adjacent).
    [  333.802149] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781048) returned 0x00000001 (completed_desc_count).
    [  333.802150] engine_reg_dump(): C2H0: ioread32(0xffffa2fbc1781090) returned 0x00f83e1e (interrupt_enable_mask)
    [  333.802151] engine_status_read(): C2H0: Status of SG DMA C2H engine:
    [  333.802153] engine_status_read(): C2H0: ioread32(0xffffa2fbc1781040).
    [  333.802155] engine_status_read(): C2H0: status = 0x00000006: IDLE DESC_STOPPED DESC_COMPLETED 
    [  333.802156] engine_service_shutdown(): C2H0: engine just went idle, resetting RUN_STOP.
    [  333.802157] xdma_engine_stop(): C2H0: xdma_engine_stop(engine=ffff934d335ace00)
    [  333.802159] xdma_engine_stop(): C2H0: Stopping SG DMA C2H engine; writing 0x00f83e1e to 0xffffa2fbc1781004.
    [  333.802160] xdma_engine_stop(): C2H0: xdma_engine_stop(C2H) done
    [  333.802162] engine_service(): C2H0: desc_count = 1
    [  333.802163] engine_service(): C2H0: head of queue transfer 0xffff934e14c2cb00 has 1 descriptors
    [  333.802164] engine_service(): C2H0: Engine completed 1 desc, 1 not yet dequeued
    [  333.802165] engine_service_final_transfer(): C2H0: engine C2H completed transfer
    [  333.802166] engine_service_final_transfer(): C2H0: Completed transfer ID = 0xffff934e14c2cb00
    [  333.802168] engine_service_final_transfer(): C2H0: *pdesc_completed=1, transfer->desc_num=1
    [  333.802171] engine_service_resume(): C2H0: no pending transfers, C2H engine stays idle.
    [  333.802173] transfer_data(): C2H0: transfer ffff934e14c2cb00 completed
    [  333.802176] transfer_data(): C2H0: remain=0, done=4096
    [  333.802177] char_sgdma_read_write(): C2H0: seq:1 char_sgdma_read_write() return=4096.
    [  333.802178] interrupt_status():reg = ffffa2fbc1782000
    [  333.802179] interrupt_status():&reg->user_int_enable = ffffa2fbc1782004
    [  333.802181] interrupt_status():user_int_enable = 0x00000001
    [  333.802182] interrupt_status():channel_int_enable = 0x00000003
    [  333.802184] interrupt_status():user_int_request = 0x00000000
    [  333.802186] interrupt_status():channel_int_request = 0x00000000
    [  333.802187] interrupt_status():user_int_pending = 0x00000000
    [  333.802189] interrupt_status():channel_int_pending = 0x00000000
    [  333.802196] char_sgdma_close(): C2H0: char_sgdma_close(0xffff934e14bee428, 0xffff934e146e3b00)
    
    展开全文
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  • 自己将Xilinx提供的xdma IP核 PCIE驱动的底层读写操作封装成了DLL文件,可供其它C++或C#程序直接调用,已经在项目中使用,非常方便,支持PCIE中断
  • XDMA驱动配置及详解

    千次阅读 2020-09-28 16:11:36
     在设备管理器中找到PCI内存设备,更新驱动程序 XDMA_Driver(整个文件夹),电脑调成测试模式   打完驱动断电重启后会出现XDMA设备 第二步:找设备并打开和关闭  通过设备实例路径来识别每一个XDMA设备,...
  • 基于xilinx vivado的XDMA IP的使用详解

    千次阅读 多人点赞 2020-10-30 10:43:26
    本文是关于XDMA ip的使用详解,主要从ip的设置与使用两方面介绍。 包括:XDMA的IP设置;XDMA的IP参数选择;中断情况;例程模式;实际实例等方面。
  • PCIe XDMA IP核读写测试

    千次阅读 热门讨论 2019-09-03 12:37:49
    使用XDMA IP核测得读写速度如下: 在进行XDMA核IP设置时,PCIe ID页无需进行更改,直接默认即可。生成bit文件下载到板卡后,重启板卡所在PC,重启后设备管理器会识别成PCIe ID页的ID。 Block Design 设计图如下 ...
  • 这是Xilinx官方提供的Windows平台下的XDMA的驱动程序和VS源代码,压缩包里面包含三个子压缩包
  • PCIe的XDMA应用

    千次阅读 2020-09-26 15:56:13
    之前介绍的PCIe实物模型为PIO模式,可编程PIO模式,软件控制CPU在主机总线上发起一个存储器或IO读写总线周期,并以映射在PCIe设备地址空间的一个地址为目标,根据PCIe总线宽度的区别,在每个...一、XDMA相关知识 绝...
  • 基于Xilinx FPGA XDMA的PCIE通信 0 概述 最近因仪表项目需求,需要上位机PC端通过PCIE接口与FPGA功能子卡进行数据通信,故开始研究基于Xilinx A7 FPGA实现PCIE接口功能。 1 准备工作 要实现上位机Host端与FPGA...
  • XC7K325T PCIE XDMA 环境搭建及测试(含教程和FPGA工程上位机),有操作教程,FPGA源码(VIVADO2017.4打开),参考原理图,资料总共396MB。
  • XDMA 异常状态(busy) 如何恢复? 使用zynq7035 xdma gen2, x8,mem模式x ,正常运行时没有问题。 c2h模式下,mem 接口是由 stream 的数据转换而来。 一旦 windows 驱动侧开启的c2h.read ,FPGA当中的stream ...
  • 本工程通过Xilinx官方的XDMA核实现上位机和PCIE的通信,通过AXI4协议实现PCIE数据和ARM核的通信。工程内使用了XDMA核(官方)、AXI4Slave核(自编)、DMA核和ARM核,实现数据的通信。
  • xilliix pcie dma 驱动 (基于 xilnx xdma ip核 4.0 的WDF驱动) --- # XDMA Windows Driver This project is Xilinx's sample Windows driver for 'DMA/Bridge Subsystem for PCI Express v4.0' (XDMA) IP. *...
  • 基于Xilinx的XDMA核实现AXI4转AXI-stream协议的数据读写工程!通过工程实例完美学习PCIE,快速入手。
  • XILINX PCIE DMA/Bridge Subsystem for PCI Express (XDMA)笔记

    万次阅读 多人点赞 2019-03-25 16:24:30
    前段时间在公司项目中调试了PCIE,正好做一个总结,那些介绍XDMA、PCIE之类的多余的东西网上能搜到很多,我这里就不多说。我写的只是自己的一些想法,以及自己的设计思路。 同每一个刚开始调试PCIE的人一样,作为...
  • 使用XDMA测试FPGA与PC通信

    千次阅读 2020-09-28 16:38:22
    使用XDMA测试FPGA与PC通信 万物皆可卷积 ​ 武汉大学 电路与系统硕士在读 19 人赞同了该文章 Xilinx的Vivado中,有三种方式可以实现PCIE功能,分别为: 调用7 Series Integrated Block for PCI Express IP核...

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