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  • 卡诺图最小化工具 V1.0 使用卡诺图最小化(参见 wikipedia.org 中的“卡诺图”)。 Python scrypt 采用一个 ASCII 文件,输出数据保存在 .asm 文件中。
  • 卡诺图 (Karnaugh Map)

    千次阅读 2021-02-27 14:58:11
    1 卡诺图的组成 几何相邻: 左右上下相接。 逻辑相邻:两个最小项只有一个变量是不同的。

    1 卡诺图的组成

    几何相邻: 左右上下相接。

    逻辑相邻:两个最小项只有一个变量是不同的。

    如何将函数化简为最简的与或非式时,可以采用合并0的方式,即且~Y的化简结果。

    函数化简时,可以通过合并卡诺图中的1得到化简结果,也可以通过合并卡诺图中的0先求出~Y的化简结果,然后再对~Y求反得到Y。

    消除1,实现与-或式;消除0,实现与-或-非式

    2 约束项 无关项 任意项

    约束项:输入不可能出现的值.

    由于每一组输入变量的取值都使一个,而且仅有一个最小项的值为1。如果要限定某些输入变量的取值不能出现时,可以用它们对应最小项恒等于0来表示。

    无关项:输入变量的某些取值下,函数值是1还是0都可以,并不会影响电路功能 (例如:优先译码器)

    展开全文
  • HDLBits(8)——Karnaugh Map to Circuit----- 73. 3-varible -----Problem StatementAnswer----- 74. 4-varible (a) -----Problem StatementAnswer----- 75. 4-varible (b) -----Problem StatementAnswer----- 76....

    ----- 73. 3-varible -----

    Problem Statement

    (三变量卡诺图)

    Implement the circuit described by the Karnaugh map below.

    在这里插入图片描述

    Answer

    一个非常容易化简的卡诺图,因此这里仅放出化简后的逻辑表达式,图就不放了:

    out’ = a’b’c’ or out = (a’b’c’)’ (撇号表示取反,乘积表示与运算,加法表示或运算)

    module top_module(
        input a,
        input b,
        input c,
        output out  ); 
        
        assign out = ~(~a & ~b & ~c);
    
    endmodule
    

    ----- 74. 4-varible (a) -----

    Problem Statement

    (四变量卡诺图)

    Implement the circuit described by the Karnaugh map below.

    在这里插入图片描述

    Answer

    在这里插入图片描述

    out = a’d’ + b’c’ + a’bc + acd

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
        assign out = (~a & ~d) | (~b & ~c) | (~a & b & c) | (a & c & d);
    
    endmodule
    

    ----- 75. 4-varible (b) -----

    Problem Statement

    (四变量带有约束条件的卡诺图)

    Implement the circuit described by the Karnaugh map below.

    在这里插入图片描述

    Answer

    在这里插入图片描述

    out = b’c + a

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
        assign out = (~b & c) | a;
    
    endmodule
    

    ----- 76. 4-varible © -----

    Problem Statement

    (四变量卡诺图)

    Implement the circuit described by the Karnaugh map below.

    在这里插入图片描述

    Answer

    (这道题貌似只能硬解,但是也有更巧妙的办法,如下所示)

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
        assign out = a + b + c + d;
    
    endmodule
    

    ----- 77. Minimum SOP and POS -----

    Problem Statement

    A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

    Determine the output out_sop in minimum SOP(Sum of Product,最小项表达式(与或式):积之和) form, and the output out_pos in minimum POS(Product of Sum,最大项表达式(或与式):和之积) form.

    Answer

    由题意画出卡诺图:

    在这里插入图片描述

    化简卡诺图:

    在这里插入图片描述

    out_sop = cd + a’b’c

    out_pos = ( (c’+ d’)·(a + b + c’) )'

    (POS式我懒得化简了。。。)

    module top_module (
        input a,
        input b,
        input c,
        input d,
        output out_sop,
        output out_pos
    ); 
        
        assign out_sop = (c & d) | (~a & ~b & c);
    	assign out_pos = ~( (~c | ~d) & (a | b | ~c) );
    
    endmodule
    

    ----- 78. Karnaugh map (a) -----

    Problem Statement

    Consider the function f shown in the Karnaugh map below.

    在这里插入图片描述

    Implement this function. d is don’t-care, which means you may choose to output whatever value is convenient.

    Answer

    在这里插入图片描述

    f = x1’x3 + x2x4

    module top_module (
        input [4:1] x, 
        output f );
        
        assign f = (~x[1] & x[3]) | (x[2] & x[4]);
    
    endmodule
    

    ----- 79. Karnaugh map (b) -----

    Problem Statement

    Consider the function f shown in the Karnaugh map below. Implement this function.

    (The original exam question asked for simplified SOP and POS forms of the function.)

    在这里插入图片描述

    Answer

    在这里插入图片描述

    f = x2’x4’ + x1’x3 + x2x3x4

    module top_module (
        input [4:1] x,
        output f
    ); 
        
        assign f = (~x[2] & ~x[4]) | (~x[1] & x[3]) | (x[2] & x[3] & x[4]);
    
    endmodule
    

    ----- 80. K-map implemented with a multiplexer -----

    Problem Statement

    (批注:比较新颖的题目,用多路选择器实现卡诺图运算。需要注意的是,题目仅要求写出c、d的实现,并且只能使用多个二选一)

    For the following Karnaugh map, give the circuit implementation(实现,执行) using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

    You are implementing(实现) just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.

    在这里插入图片描述

    在这里插入图片描述

    (The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers with constant inputs. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.)

    Answer

    (本题思路灵感来源于《FPGA原理和结构》P57,可查阅“香农展开定理”)

    先说一下初步的思路:观察卡诺图,可以这么看,当cd = 00时,mux[3:0] = 0100(注意卡诺图的顺序和代码的不一致);当cd = 01时,mux[3:0] = 0001;当cd = 10时,mux[3:0] = 0101;当cd = 11时,mux[3:0] = 1001

    初步思路有了以后,其实大家已经发现了,这就是一个类似于选择器一样的东西,即输入cd,根据cd的值来输出对应mux的值。不过问题在于,我们要使用的是二选一选择器,而且应该至少要使用4个吧。列出表总结一下:

    cdmux[3] (f3)mux[2] (f2)mux[1] (f1)mux[0] (f0)
    000100
    010001
    100101
    111001

    接着我们照表写出四个逻辑表达式:

    f3 = cd

    f2 = c’d’ + cd’ = d’

    f1 = 0 (这个最简单了嘿嘿)

    f0 = (c’d’)’ = c + d

    然后需要将以上四个逻辑表达式化为二选一表达式(即f = sel’·a + sel·b的形式):

    f3 = c·d (对照二选一表达式:sel = c, a = 0, b = d)

    f2 = d’ (对照二选一表达式:sel = d, a = 1, b = 0)

    f1 = 0 (不需要使用选择器了)

    f0 = c + d (暂时还想不到用二选一实现的办法,直接用或门吧)

    最后实现电路:

    module top_module (
        input c,
        input d,
        output [3:0] mux_in
    ); 
        
         mux21 ex3(.sel(c), .a(0), .b(d), .out(mux_in[3]));
    	 mux21 ex2(.sel(d), .a(1), .b(0), .out(mux_in[2]));
    	 assign mux_in[1] = 0;
    	 assign mux_in[0] = c | d;
    
    endmodule
    
    module mux21 (
    	input sel,
    	input a, b,
    	output reg out
    );
    	always @(*) begin
    		case(sel)
    			1'b0: out = a;
    			1'b1: out = b;
    		endcase
    	end		
    endmodule
    
    展开全文
  • endmodule 3.1.4 Karnaugh Map to Circuit 1. 3-variable module top_module( input a, input b, input c, output out ); assign out=a|b|c; endmodule 2. 4-variable module top_module( input a, input b, ...

    目录

    3.Circuits

    3.1 Combinational Logic

    3.1.2  Multiplexers

    1. 2-to-1 multiplexer

    2. 2-to-1 bus multiplexer

    3. 9-to-1 multiplexer

    4. 256-to-1 multiplexer

    5. 256-to-1 4-bit multiplexer

    3.1.3  Arithmetic Circuits

    1. Half adder

    2. Full adder

    3. 3-bit binary adder

    4. Adder

    5. Signed addition overflow

    6. 100-bit binary adder

    7. 4-digit BCD adder

    3.1.4 Karnaugh Map to Circuit

    1. 3-variable

    2. 4-variable

    3. 4-variable

    4. 4-variable

    5. Minimum SOP and POS

    6. Karnaugh map

    7. Karnaugh map

    8. K-map implemented with a multiplexer


    HDLBits网站地址:HDLBits

    3.Circuits

    3.1 Combinational Logic

    3.1.2  Multiplexers

    1. 2-to-1 multiplexer

    Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

    module top_module( 
        input a, b, sel,
        output out ); 
        
    	assign out=sel?b:a;
        
    endmodule

    2. 2-to-1 bus multiplexer

    Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

    module top_module( 
        input [99:0] a, b,
        input sel,
        output [99:0] out );
        
    	assign out=sel?b:a;
          
    endmodule

    3. 9-to-1 multiplexer

    Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

    module top_module( 
        input [15:0] a, b, c, d, e, f, g, h, i,
        input [3:0] sel,
        output [15:0] out );
    
        always @(*) begin
            case (sel) 
                 4'd0:out=a;
                 4'd1:out=b;
                 4'd2:out=c;
                 4'd3:out=d;
                 4'd4:out=e;
                 4'd5:out=f;
                 4'd6:out=g;
                 4'd7:out=h;
                 4'd8:out=i;
                default:out=16'hffff;
            endcase
        end
        
        
    endmodule

    4. 256-to-1 multiplexer

    Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

    module top_module( 
        input [255:0] in,
        input [7:0] sel,
        output out );
    
        assign out=in[sel];
    
        
    endmodule

    5. 256-to-1 4-bit multiplexer

    Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

    //in[sel*4+:4]    sel*4+:4  相当于 sel*4+3:sel*4  ,但是这样写不对。

    module top_module( 
        input [1023:0] in,
        input [7:0] sel,
        output [3:0] out );
        
        assign out=in[sel*4+:4];  
        
        
    endmodule

    3.1.3  Arithmetic Circuits

    1. Half adder

    半加器

    Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

    module top_module( 
        input a, b,
        output cout, sum );
        
        assign {cout,sum}=a+b;
        
    endmodule
    

    2. Full adder

    全加器,输入多了进位。

    Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

    module top_module( 
        input a, b, cin,
        output cout, sum );
        
        assign {cout,sum}=a+b+cin;
        
    endmodule

    3. 3-bit binary adder

    Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder. The adder adds two 3-bit numbers and a carry-in to produce a 3-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[2] is the final carry-out from the last full adder, and is the carry-out you usually see.

    module top_module( 
        input [2:0] a, b,
        input cin,
        output [2:0] cout,
        output [2:0] sum );
        
        assign sum[0]=a[0]^b[0]^cin;
        assign sum[1]=a[1]^b[1]^cout[0];
        assign sum[2]=a[2]^b[2]^cout[1];
        assign cout[0]=(a[0]&b[0]) | (a[0]&cin) | (b[0]&cin);
        assign cout[1]=(a[1]&b[1]) | (a[1]&cout[0]) |( b[1]&cout[0]);
        assign cout[2]=(a[2]&b[2]) | (a[2]&cout[1]) | (b[2]&cout[1]);
        
    endmodule

    4. Adder

    module top_module (
        input [3:0] x,
        input [3:0] y, 
        output [4:0] sum);
      assign sum=x+y;
    endmodule

    5. Signed addition overflow

    Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

    溢出只有两种情况:正+正=负,负+负=正,所以就不需要考虑两个输入的符号位不同的情况。

    module top_module (
        input [7:0] a,
        input [7:0] b,
        output [7:0] s,
        output overflow
    ); //
     
        // assign s = ...
        // assign overflow = ...
        assign s=a+b;
        assign overflow=(s[7]&~a[7]&~b[7]) | (~s[7]&b[7]&a[7]);
       
    endmodule

    6. 100-bit binary adder

    Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.

    module top_module( 
        input [99:0] a, b,
        input cin,
        output cout,
        output [99:0] sum );
        
        assign {cout,sum}=a+b+cin;
        
    endmodule

    7. 4-digit BCD adder

    You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

    module bcd_fadd {
        input [3:0] a,
        input [3:0] b,
        input     cin,
        output   cout,
        output [3:0] sum );
    

    Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. Your adder should add two 4-digit BCD numbers (packed into 16-bit vectors) and a carry-in to produce a 4-digit sum and carry out.

    module top_module( 
        input [15:0] a, b,
        input cin,
        output cout,
        output [15:0] sum );
      wire  [3:0]  cc;		//连接cin和前一个cout
        //实例化第一个模块
        bcd_fadd bcd_fadd_inst(
            .a 		(a[3:0]),
            .b 		(b[3:0]),
            .cin	(cin)	  ,
            .cout	(cc[0])	  ,
            .sum	(sum[3:0])
        );
        
        //由generate生成的模块
        generate 
            genvar i;
            for (i=1;i<4;++i) begin : bcd_fadd1
                bcd_fadd bcd_fadd_inst(
                    .a	  (a[(7+4*(i-1)):(4+4*(i-1))]),
                    .b	  (b[(7+4*(i-1)):(4+4*(i-1))]),
                    .cin  (cc[i-1]),
                    .cout (cc[i]),
                    .sum  (sum[(7+4*(i-1)):(4+4*(i-1))]) 
                ); 
            end
        endgenerate
        
        assign cout = cc[3];
         
    endmodule

    3.1.4 Karnaugh Map to Circuit

    1. 3-variable

     

    module top_module(
        input a,
        input b,
        input c,
        output out  ); 
    assign out=a|b|c;
    endmodule

    2. 4-variable

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
     //   assign out=(~b&~c)|(~a&~b&c&~d)|(~a&b&c)|(a&c&d)|(~a&b&~c&~d);
        assign out=(~b&~c)|(~a&~d)|(~a&b&c)|(a&c&d);
    endmodule

     

    3. 4-variable

    根据卡诺图写出公式,并进行化简,得到最简公式,再进行写代码。 

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
        
        assign out=((c&~b)|(a&b&c)|(a&~c&~d))?1'b1:((~a&b&~c&~d)|(a&~c&d))?d:1'b0;
    
    endmodule

    4. 4-variable

    Implement the circuit described by the Karnaugh map below.

    Kmap4.png

    Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

    化简半天,没正确,直接写出所有情况了。

    module top_module(
        input a,
        input b,
        input c,
        input d,
        output out  ); 
        
        
       assign out = ~a & b & ~c & ~d | a & ~b & ~c & ~d | 
            		 ~a & ~b & ~c & d | a & b & ~c & d | 
            		 ~a & b & c & d | a & ~b & c & d | 
            		 ~a & ~b & c & ~d | a & b & c & ~d;
    
    
    endmodule

    5. Minimum SOP and POS

    A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

    Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.

    module top_module (
        input a,
        input b,
        input c,
        input d,
        output out_sop,
        output out_pos
    ); 
        
        assign out_sop = c & d | ~a & ~b & c;
        assign out_pos = ~((~c | ~d) & (a | b | ~c));
    
    endmodule

    6. Karnaugh map

    module top_module (
        input [4:1] x, 
        output f );
        
        assign  f=(~x[1]&x[3])|(x[1]&x[2]&~x[3]&x[4]);
    
    endmodule

    7. Karnaugh map

    module top_module (
        input [4:1] x,
        output f
    ); 
    
        assign f = ~x[1] & x[3] | x[2] & x[3] & x[4] | ~x[2] & ~x[4];
        
    endmodule

    8. K-map implemented with a multiplexer

    按照ab的四种组合进行选择,4选1的四种选择对应的就是mux_in的四位状态。

    module top_module (
        input c,
        input d,
        output [3:0] mux_in
    ); 
        
        assign mux_in[0] = c ? 1'b1 : d;
        assign mux_in[1] = 1'b0;
        assign mux_in[2] = d ? 1'b0 : 1'b1;
        assign mux_in[3] = c ? d : 1'b0;
    
    endmodule

     

    展开全文
  • Exams/ece241 2013 q2:Minimum SOP and POS 题目链接为: Exams/ece241 2013 q2 问题描述 具有四个输入 (a,b,c,d) 的单输出数字系统在输入出现2、7 或 15 时产生逻辑 1,当输入出现 0、1、4、5、6、9、10、13或...

    Exams/ece241 2013 q2:Minimum SOP and POS

    题目链接为:

    Exams/ece241 2013 q2

    问题描述

    具有四个输入 (a,b,c,d) 的单输出数字系统在输入出现 2、7 或 15 时产生逻辑 1,当输入出现 0、1、4、5、6、9、10、13或14 时产生逻辑 0 。数字 3、8、11 和 12 的输入条件从未出现在此系统中。例如,7 对应于分别设置a,b,c,d为0、1、1、1。确定最小SOP形式的输出out_sop,以及最小POS形式的输出out_pos。

    问题解答

    (1)根据题意可以画出如下卡诺图:

    (2)随后进行卡诺图的化简:

            最小SOP:

            采用圈1法,如图中蓝色和绿色实线所示,合并标1的最小项,即L=cd+\bar{a}\bar{b}c

            最小POS:

            采用圈0法,如图中红、黄、深蓝色虚线所示,合并标0的最小项,得到\bar{L}=\bar{c}+bc\bar{d}+ac\bar{d}

    通过将该逻辑表达式进行化简,可以得到L=c\cdot (\bar{b}+\bar{c}+d)\cdot(\bar{a}+\bar{c}+d)

    得到该卡诺图的逻辑表达式后,便可以开始编写verilog代码。

    module top_module (
        input a,
        input b,
        input c,
        input d,
        output out_sop,
        output out_pos
    ); 
        
        assign out_sop = (c&d)|(~a&~b&c);        //sop
        assign out_pos = c&(~b|~c|d)&(~a|~c|d);  //pos
    
    endmodule
    

    Exams/m2014 q3 Karnaugh map

    题目链接为:

    Exams/m2014 q3

    问题描述

    得出下面卡诺图中显示的函数 f。

    File:Exams m2014q3.png

     问题解答

    采用圈0法,如下图所示。

     合并标0的最小项,得到\bar{L}=\bar{x_{1}}\bar{x_{3}}+\bar{x_{3}}\bar{x_{4}}+x_{1}\bar{x_{2}}+x_{1}x_{3},将该表达式化简,可以得到:

    L=(x_{1}+x_{3})\cdot(x_{3}+x_{4})\cdot(\bar{x_{1}}+x_{2})\cdot(\bar{x_{1}}+\bar{x_{3}})。得到该卡诺图的逻辑表达式后,便可以开始编写verilog代码。

    module top_module (
        input [4:1] x, 
        output f );
    
        assign f = (x[1]|x[3])&(x[3]|x[4])&(~x[1]|x[2])&(~x[1]|~x[3]);
        
    endmodule

    Exams/2012 q1g Karnaugh map

    题目链接为:

    Exams/2012 q1g

    问题描述

    得出下面卡诺图中显示的函数 f。(原试题要求简化 SOP 和 POS 形式的函数。)

    File:Exams 2012q1g.png

     问题解答

        最小SOP:采用圈1法,如下图所示。

    合并标1的最小项,得到L=\bar{x_{2}}\bar{x_{4}}+\bar{x_{1}}x_{3}+x_{2}x_{3}x_{4}

         最小POS:采用圈0法,如下图所示。

    合并标0的最小项,得到\bar{L}=\bar{x_{3}}\bar{x_{4}}+x_{2}\bar{x_{3}}+x_{1}x_{2}\bar{x_{4}}+x_{1}\bar{x_{2}}x_{4},通过化简该逻辑表达式,可以得到:L=(x_{3}+\bar{x_{4}})\cdot(\bar{x_{2}}+x_{3})\cdot(\bar{x_{1}}+\bar{x_{2}}+x_{4})\cdot(\bar{x_{1}}+x_{2}+\bar{x_{4}})。得到该卡诺图的逻辑表达式后,便可以开始编写verilog代码。

    module top_module (
        input [4:1] x,
        output f
    ); 
        
        //assign f = (~x[2]&~x[4])|(~x[1]&x[3])|(x[2]&x[3]&x[4]);                     //sop
        assign f = (x[3]|~x[4])&(~x[2]|x[3])&(~x[1]|~x[2]|x[4])&(~x[1]|x[2]|~x[4]);   //pos
    
    endmodule

     

    展开全文
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