Vivado Design Suite HLx Editions - Accelerating High Level Design 加速高层次设计

Vivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.
The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.
Accelerating High Level Design

Software-defined IP Generation with Vivado High-Level Synthesis 使用vivado高级综合生成软件定义IP

Block-based IP Integration with Vivado IP Integrator 使用vivado IP集成器完成基于模块的IP集成

Model-based Design Integration with Model Composer and System Generator for DSP

Accelerating Verification 加速验证

Vivado Logic Simulation vivado逻辑仿真

Integrated Mixed Language Simulator 集成混合语言仿真器

Integrated & Standalone Programming and Debug Environments

Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS

Verification IP 验证IP

Accelerating Implementation 加速执行

4X Faster Implementation

20% Better Design Density

Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end


如何向vivado中添加约束constraints？

关于constraints文件的格式: XDC(Xilinx Desin Constraints)约束文件

详情参看文档：ug945-vivado-using-constraints-tutorial  以及 ug903-Vivado Design Suite User Guide：Using Constraints

organize constraints: Timing Constraints, Physical Constraints

constraints sets and files

placement constraints

Set as Target Constraint File

Vivado Timing Constraints Wizard

Edit Timing Constraints

design check point(DCP) modes

不支持legacy user constraints file(UCF) format

synopsys design constraints(SDC)

tcl semantic

window > timing constraints > edit timing constraints

create_clock

create_generated_clock

set_input_delay

set_output_delay

set_clock_groups

set_false_path

set_max_delay

set_multicycle_path

How to write XDC files?


How to write and use testbench?

testbench syntax


vivado的软件开发流程：



(1) UG973-Release Notes, Installation, and Licensing 
     宿舍电脑新安装的2018.2版本license存在问题，而且不支持全部器件（问题待解决）
(2) UG949-UltraFast Design Methodology Guide for the Vivado Design Suite
     超高速设计方法学？
(3) UG1231-UltraFast Design Methodology Quick Reference Guide
     介绍了FPGA从PCB到设计分析的完整流程。
(4) UG1197-UltraFast High-Level Productivity Design Methodology Guide
     从系统以及基于C语言的角度来介绍设计方法。
(5) UG1270-Vivado HLS optimization Methodology Guide
     HLS的方法，未深入学习，先做标注。
(6) UG1046-UltraFast Embedded Design Methodology Guide
     FPGA的嵌入式应用
(7) UG1026-UltraScale Architecture Migration
     器件的移植，可能在应用中会接触到。此外提问7系列与UltraScale器件的区别
(8) UG998-Introduction to FPGA Design with Vivado High-Level Synthesis
     HLS设计的介绍
(9) UG911-ISE to Vivado Design Suite Migration Guide
     ISE至vivado的转移：没有用过ISE
(10) UG1192-Xilinx Design Flow for Intel FPGA and SoC Users
     Intel与Xilinx的应用转换，还附有几个设计代码。


(11) UG910-Vivado Design Suite User Guide:Getting Started
     上手设计的介绍性文档，内容简略。
(12) UG892-Vivado Design Suite User Guide：Design Flows Overview
     设计流程概述
(13) UG893-Vivado Design Suite User Guide：Using the Vivado IDE
     vivado集成开发环境的设置和操作
(14) UG894-Vivado Design Suite User Guide：Using Tcl Scripting
     tcl命令
(15) UG895-Vivado Design Suite User Guide：System-Level Design Entry
     系统级设计方法
(16) UG896-Vivado Design Suite User Guide：Designing with IP
     基于IP的设计方法
(17) UG1118-Vivado Design Suite User Guide：Creating and Packaging Custom IP
     创建以及封装用户定制IP
(18) UG994- Vivado Design Suite User Guide:Designing IP Subsystems Using IP Integrator
     利用 IP集成器？来设计IP子系统
(19) UG898-Vivado Design Suite User Guide：Embedded Processor Hardware Design
     FPGA作为嵌入式处理器的硬件设计（没有看到PCB信息，应该是系统级，稍后学习）
(20) UG897-Vivado Design Suite User Guide: Model-Based DSP Design Using System Generator
     Matlab System Generator工具进行FPGA数字信号处理设计
(21) UG1262-Model Composer User Guide
     暂时还未接触过Model Composer
(22) UG902-Vivado Design Suite User Guide: High-Level Synthesis
     HLS详细的指南
(23) UG899-Vivado Design Suite User Guide：I/O and Clock Planning
     I/O以及时钟规划
(24) UG900-Vivado Design Suite User Guide：Logic Simulation
     逻辑仿真方法：对于验证来说比较重要
(25) UG440-Xilinx Power Estimator User Guide
     功耗估计器？
(26) UG903-Vivado Design Suite User Guide: Using Constraints
     使用约束
(27) UG901-Vivado Design Suite User Guide：Synthesis
     综合
(28) UG904-Vivado Design Suite User Guide：Implementation
     执行？
(29) UG905-Vivado Design Suite User Guide：Hierarchical Design
     层次设计
(30) UG909-Vivado Design Suite User Guide: Partial Reconfiguration
     部分重配置？
(31) UG907-Vivado Design Suite User Guide: Power Analysis and Optimization
     功率分析以及最优化
(32) UG906-Vivado Design Suite User Guide：Design Analysis and Closure Techniques
     设计分析以及环路？技术
(33) UG908-Vivado Design Suite User Guide：Programming and Debugging
     向FPGA中编程以及调试


(34) UG975-Vivado Design Suite Quick Reference
     vivado设计的快速指南
(35) UG835-Vivado Design Suite Tcl Command Reference Guide
     tcl命令
(36) UG912-Vivado Design Suite Properties Reference Guide 
     各类参数
(37) UG953-Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide
     7系列FPGA以及Zynq的库
(38) UG974-UltraScale Architecture Libraries Guide
     ultrascale架构库
(39) UG958-Vivado Design Suite Reference Guide：Model-Based DSP Design Using System Generator
     使用System Generator工具
(40) UG984-MicroBlaze Processor Reference Guide
      MicroBlaze软核
(41) Quick Start Guide: MicroBlaze Soft Processor Presets
      MicroBlaze软核的快速入门
(42) UG1138-Generating Basic Software Platforms Reference Guide
      软件环境？
(43) UG1037-Vivado Design Suite AXI Reference Guide
     AXI总线


(44) UG888-Vivado Design Suite Tutorial Design Flows Overview
     设计流程指南
(45) UG939-Vivado Design Suite Designing with IP Tutorial
      IP指南
(46) UG1119-Vivado Design Suite Creating, Packaging Custom IP Tutorial
     创建，封装定制IP指南
(47) UG995-Vivado Design Suite Tutorial Designing IP Subsystems Using IP Integrator
     通过IP集成器？进行IP子系统设计指南
(48) UG940-Vivado Design Suite Tutorial Embedded Processor Hardware Design
     嵌入式处理器硬件设计指南
(49) UG1209-Zynq UltraScale+ MPSoC: Embedded Design Tutorial A Hands-On Guide to Effective Embedded System design   Zynq UltraScale+高效嵌入式系统设计指南
(50) UG1165-Zynq-7000 All Programmable SoC: Embedded Design Tutorial A Hands-On Guide to Effective Embedded System Design   Zynq 7000高效嵌入式系统设计指南
(51) UG871-Vivado Design Suite Tutorial High-Level Synthesis
     HLS指南
(52) UG948-Vivado Design Suite Tutorial Model-Based DSP Design Using System Generator
     System Generator指南
(53) UG1259-Tutorial: Model-Based Design Using Model Composer
     Model Composer指南
(54) UG937-Vivado Design Suite Tutorial Logic Simulation
     逻辑仿真指南
(55) UG945-Vivado Design Suite Tutorial Using Constraints
     约束指南
(56) UG986-Vivado Design Suite Tutorial Implementation
     执行指南
(57) UG947-Vivado Design Suite Tutorial Partial Reconfiguration
     部分重配置指南
(58) UG938-Vivado Design Suite Tutorial Design Analysis and Closure Techniques
     设计分析与环路？技术指南
(59) UG997-Vivado Design Suite Tutorial Power Analysis and Optimization
     功率分析以及最优化指南
(60) UG936-Vivado Design Suite Tutorial Programming and Debugging
     对FPGA编程以及调试指南
(61) UG1198-Vivado Design Suite Tutorial Revision Control Systems
     修订控制系统指南？



Tutorial：design flow 设计流程简单指南，目的是掌握FPGA vivado操作基本要点

project file(.xpr)

tcl command: read_verilog, read_vhdl, read_edif, read_ip, read_xdc, create_project, add_files, import_files, add_directories,  synth_design, opt_design, place_design, route_design, write_bitstream, launch_runs 针对命令模式下的工程设计

some examples: <Vivado_install_area>/Vivado//examples/Vivado_Tutorial 有许多示例，在此标注

Synthesizing the Design>>Defining Timing Constraints and I/O Planning>>Exporting the Modified Constraints>>Implementing the Design>>Opening a Design Checkpoint?

window>timing constraints

window>package; layout selector>I/O planning

reports>timing>report timing summary

running behavioral simulation: 详细参看logic simulation

注意设置: Settings

synthesizing and implementing the design: generate bitstream

analyze synthesized design(how? what’s the point?), analyze implemented design

IOSTANDARD


Tutorial：logic simulation

parsers？

behavioral, functional, timing simulation

snapshot?

debouncer?

DDS compiler for sine wave

FSM: finite state machine

UG937-design files directory

Kintex-7 KC705 Evaluation Platform for 7-Series or Kintex-UltraScale KCU105 Evaluation Platform

Functional and timing simulations are available post-synthesis and post-implementation

added IP from the Xilinx IP catalog and generated IP outputs needed for simulation

configure the wave window

breakpoints


仿真时出现的问题：

(1) vivado仿真出错：[USF-XSim 62] ‘compile’ step failed with error(s) while executingvivado仿真出错：[USF-XSim 62] ‘compile’ step failed with error(s) while executing 解决方案：改正逻辑文件中的错误–变量名称写错


Tutorial: Using Constraints

Timing constraints，physical constraints

Create a constraint set and set a target constraint file

add timing constraints to a design using the Timing Constraints Wizard

add timing exceptions using the Timing Constraints Editor

saving constraints to disk versus in-memory constraints ？

generate the clock interaction report and properly interpret the resulting matrix

generate the timing summary report and properly interpret the results

primary clock, multicycle path

synthesized design > report clock interaction

reports > timing > report timing summary

worst negative stack > F4 >schematic

netlist, device

layout > I/O planning

pin select > set prohibit > unusable

placement constraints

添加时序，禁用IO等约束，具体细节再理清


Tutorial: Implementation

define multiple implementation runs to employ different strategies to resolve timing

flow > create runs

strategy: performance_explore, flow_RunPhysOpt, Flow_RuntimeOptimized

using incremental compile

BFT design

impl_1 > open Run Directory

get_property DIRECTORY [current_run]

set incremental compile

get_property INCREMENTAL_CHECKPOINT [current_run]

此处出现了一个错误，没有解决：

[Common 17-165] Too many positional options when parsing ‘’, please type ‘iphys_opt_design -help’ for usage info.

run the Incremental Compile flow

using a checkpoint from a previously implemented design

examining the Incremental Reuse Report

Analyzed the clock skew on the output data bus using the Report Datasheet command.

Used manual placement techniques to improve the timing of selected nets.

Used the Assign Manual Routing Mode in the Vivado IDE to precisely control the routing of a net.

Used the FIXED_ROUTE property to copy the relative fixed routing among similar nets to control the routing of the critical portion of the nets.

内容比较多，继续看。


Tutorial: Design with IP

DCP: design checkpoint

Select and customize an IP from the IP catalog.

Instantiate the customized IP into an HDL design

Use some details of the output products required to support the IP in the design flow.

memories&storage element>FIFOs>FIFO generator

IP Documentation

show disable ports

OOC (out-of-context) module

instantiation template: VEO file

create_ip,set_property,generate_target,create_ip_run,launch_runs

stub files

IP source

XCI file


Tutorial: Custom IP

constraints defined in XDC file

standalone design

constraints: create_clock, set_max_delay

parent design provides clock

sources: constriants, design sources, simulation sources

out-of-context files

XDC files: USE_IN, PROCESSING_ORDER…

set_property USE_IN {synthesis implementation out_of_comtext} \ [get_files uart_top_ooc.xdc]


Tutorial: Design IP Subsystems using IP integrator


Tutorial: HLS

C, C++, systemC–>(high-level synthesis)–>RTL implementation

RAM, FIFO, AXI4-Stream

arbitrary precision types

DCT function


Tutorial: Model-based DSP design using system generator


Tutorial: Model-based design using model composer

model composer


Tutorial: partial reconfiguration(PR)


Tutorial: design analysis and closure techniques

design rules checker

waiver mechanisim

clock domain crossing (CDC)

design rule check (DRC)

CDC report, CDC violation


Tutorial: power analysis and optimization

reports > report power

switching activity values file (SAIF)


Tutorial: programming and debugging

integrated logic analyzer (ILA)


前言节选自： https://www.xilinx.com/ 感谢FPGA大鳄！

参考资料：

[1] Vivado开发工具熟悉之XDC约束文件: https://blog.csdn.net/celery1124/article/details/42773355

[2] Vivado使用误区与进阶: XDC约束技巧—CDC篇: http://blog.chinaunix.net/uid-29778327-id-4561035.html

[3] Xilinx资深FAE现身说教:在FPGA设计环境中加时序约束的技巧: http://blog.chinaunix.net/uid-29778327-id-4550759.html

[4] Verilog testbench总结(一): https://blog.csdn.net/wordwarwordwar/article/details/53885209

1.vivado可以不点综合，直接simulation.

2.生成ip核需导入.coe文件时，更改.coe文件内容，可以不用重新配置ip核。

3.rom核，地址和输出可能不一样。原因：有延迟，输出较地址落后1~3个clock.改进办法：地址早几个clk.

Verilog HDL模块化设计
https://blog.csdn.net/shaoyu0831/article/details/73695409
程序固化
https://blog.csdn.net/sinat_15674025/article/details/84535754

生成固化烧录：

https://blog.csdn.net/baidu_25816669/article/details/89403331

说明一下：

 1）有些安装包有很多压缩包，这些压缩包是一个压缩文件，因为太大所以分卷压缩才能上传网盘，下载所有的压缩包后解压   “.part1.rar”  结尾的压缩包，自动解压所有文件。

2）.rar  的压缩包用WinRAR软件解压，其他解压软件容易出错。


	
vitis 2020.1
	
链接：https://pan.baidu.com/s/1gsp-IruuqsothElEx_KnFw 

提取码：sere

下载所有的包，只解压红框中的压缩包




	
vitis 2019.2 
	
链接：https://pan.baidu.com/s/1Nxm7sJDnWg-w6DtFFqjauQ 

提取码：l9pt


	
vivado hls 2019.1 
	
链接：https://pan.baidu.com/s/1ZpTm84zxgAWbPSALE6t3HQ 

提取码：ny3p


	
vivado2018.3 sdx套件
	
链接：https://pan.baidu.com/s/1DLbyyFdxKgUzdNkP8KpWCQ 

提取码：sw5a


	
vivado2018.2 sdk套件
	
链接：https://pan.baidu.com/s/1uxn4yfDd-sjlbsHlg1R_2g 

提取码：shvw 

复制这段内容后打开百度网盘手机App，操作更方便哦


	
vivado2017.4 sdx套件
	
链接：https://pan.baidu.com/s/1Jh7j5wrfEo-2GNJvJAcFfg 

提取码：uj1e 

复制这段内容后打开百度网盘手机App，操作更方便哦


	
vivado license
	
适用版本：适用于Vivado 2037年版 之前的任何版本

链接：https://pan.baidu.com/s/1WbIsnTZ0lNwK46km_U4Wfg 

提取码：w53y 

复制这段内容后打开百度网盘手机App，操作更方便哦

 

有些没有及时更新，需要其他的版本的可以留言；

如有连接失效，需要到公众号里面获取！！

 

欢迎关注我的公众号：芯王国，有更多的FPGA&数字IC的技术分享，还可以获取开源FPGA项目！