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  • 海思Hi3531D芯片SDK开发包分享下载,Hi3531D芯片全套开发资料,Hi3531D V100R001C02SPC040
  • 整理对比了三个海思编解码处理芯片的详细参数,供设计选型使用 整理对比了三个海思编解码处理芯片的详细参数,供设计选型使用 整理对比了三个海思编解码处理芯片的详细参数,供设计选型使用
  • 基于海思芯片Hi3531d的PCIE从机(EP)模式的调试经验,使用windows版本的windriver工具进行寄存器读写、数据帧发送与读取测试。
  • Hi3531D V100SDK 为TXT文档百度云盘链接
  • Hi3531D V100R001C02SPC040 sdk 百度云下载

    热门讨论 2018-06-19 14:56:41
    Hi3531D V100 sdk 百度云下载 海思开发Hi3531D V100R001C02SPC040最新更新的040版,有需要的朋友可以下载学习使用。
  • hi3531D GPIO驱动

    2018-08-13 13:23:10
    hi3531D GPIO应用程序。包括代码,编译脚本。。。。。
  • Hi3531D V100R001C02SPC040

    2018-09-06 09:13:13
    海思 Hi3531D V100R001C02SPC040 SDK开发包,欢迎大家下载学习交流
  • Hi3531D V100 sdk 百度云下载 海思开发Hi3531D V100R001C01SPC040 最新更新的040版,有需要的朋友可以下载学习使用。
  • 3531——7842HDMI部分、、、、
  • Hi3531D V100R001C02SPC030

    2018-10-31 10:26:36
    Hi3531D V100R001C02SPC030百度网盘下载地址
  • 海思 3531D 040 最新版本 SDK Hi3531D V100R001C02SPC040
  • Hi3531D V100R001C01SPC030

    2018-10-31 10:25:14
    Hi3531D V100R001C01SPC030百度网盘下载地址
  • Hi3531D V200是针对多路高清/超高清(1080p/4M/5M/4K)DVR产品应用开发的新一代专业SoC芯片。Hi3531D V200集成 了ARM A53四核处理器和性能强大的神经网络推理引擎,支持多种智能算法应用。同时,Hi3531D V200还集成...
  • hi3531\3531a\3531d\3536\3536d\3559\3559a\3519 SDK下载,一网打尽
  • Hi3531DV100 硬件设计用户指南.pdf
  • 本文档主要介绍 Hi3531AV100 芯片的常用 DDR 配置的修改方法。本文档(本指南)主要适用于以下工程师: 技术支持工程师 单板硬件开发工程师
  • Hi3531D 4K VI 参数

    千次阅读 2019-05-27 14:04:39
    最近调试Hi3531D 4K输入,出现偏色,对VI和VPSS的参数进行各种调整,但都没能解决。后来在网上买了一片开发板,他们能接5个4K。运行他们自带的Encoder软件,用cat /proc/umap/vi发现了一些端倪,于是按照他们的VI...

           最近调试Hi3531D 4K输入,出现偏色,对VI和VPSS的参数进行各种调整,但都没能解决。后来在网上买了一片开发板,他们能接5个4K。运行他们自带的Encoder软件,用cat /proc/umap/vi发现了一些端倪,于是按照他们的VI配置修改了海思的sample程序,结果就正常了。

         他们的Encoder软件还是开源的呢,不过对我来说没有意义,我们公司希望自己造轮子。有兴趣的可以下载他们的Encoder看看:https://gitee.com/LinkPi/Encoder

    展开全文
  • 3531——7842HDMI部分、、、、
  • 海思SDK ,Hi3531D_V100R001C02SPC,仅用于学习交流,链接为百度云下载,完整的SDK文件,文件无损坏,可放心使用
  • 就拿Hi3531D来说,数据手册(Datasheet)上说它可以做8路1080p@30的H264/H265编码,但实际测试能做12路1080p@30的H264/H265编码。当听到这个消息时,我觉得他太新奇了,不只是国内的大多企业,就算国外的企业,也是...

    1. 为啥要做这个评测?

    某天在某聊天群里,听行家们在高谈阔论,其中一条信息炸开了我的眼球:某为是良心企业,对外说自己是80分,其实是100120分,不像大部分的企业,对外说自己是100分,其实只有7080分。就拿Hi3531D来说,数据手册(Datasheet)上说它可以做8路1080p@30的H264/H265编码,但实际测试能做12路1080p@30的H264/H265编码。当听到这个消息时,我觉得他太新奇了,不只是国内的大多企业,就算国外的企业,也是通常是吹嘘自己的能力,在宣传上夸大自己的性能指标。多年以前,我们使用TI达芬奇DM6467方案,手册上吹嘘能做4路D1的H264编码,结果我们实际做的时候,用原厂评估的库,勉强能做3路D1,后购买了印度佬细心优化过的收费的编码库,勉强能做4路的D1,但帧率经常不足25fps,尤其是输入信号源画面变化比较大的时候,帧率就不足25fps了。因此现在听说有这样的良心企业,自己决定实际去测试一下,看看群里行家是忽悠人还是真有其事,要是是真的,中国有某为这样的企业真是国之有幸啊!
        在淘宝上搜素3531d开发板或者海思开发板,出来很多很多产品,看来用某为芯片的企业还真不少啊!对比了多家之后,决定采购这家公司的产品,因为他们自带的软件能比较方便地评估出Hi3531D的各种绝技,购买链接如下:
        https://item.taobao.com/item.htm?spm=a1z10.5-c-s.w4002-22796185927.19.4c5368bcVitKqk&id=619022947575

    上面的链接是成品,不提供开发资料。下面这个链接是开发板的,厂家会提供开发资料,有SDK和Encoder源码等:
        https://shop66907778.taobao.com/category-716218460.htm?spm=2013.1.w4010-22796185914.8.af5120442Q6r9q&search=y&catName=%BF%AA%B7%A2%B0%E5#bd

    你要是个软件开发者,不防移步去看看他们的SDK以及基于SDK编写Encoder源码,我们在这篇文章中使用的软件就是他们的Encoder软件。有了这个Encoder源码,你要做hdmi编码器就基本上不用再做开发了,也许他们的思路就是闭源硬件开源软件吧。

    2. 编码性能

    2.1 12路1080p@30编码能力

    由于购买的产品只有5个HDMI输入口,为了能做12路编码测试,我们用另外7个网络流进行解码然后再进行编码(转码),这样就可以测试12路同时编码了(还顺带测试了7路网络流的解码,数据手册上说可以做8路同时解码,但实际也能做到12路1080p@30解码)。
        在这里插入图片描述
    上图可以看到前面5路是HDMI输入的,输入的信号是1080p@60,编码时可以做1080p@60输出,但为了测试传说中同时12路1080p@30 H264/H265编码能力,我们设置输出为1080p@30。后面7路是网络流(1080p@30)转码:
    在这里插入图片描述
        配置好以后,请系好安全带,马上就要空中发射火箭了,不是直飞苍穹,就是堕落大地,反正很刺激。上图(cat /proc/umap/venc):
    在这里插入图片描述
        数一数红色的框,有多少个?12个?没错,是12个!!!,而且帧率在29~31之间!看到这,你服了吗?不管你服不服,反正我服了😄。再往下看看还有啥黑科技。

    2.2 2路4K@30(3840x2160)编码+4路1080p@30编码能力

    购买的产品只有5个HDMI输入口,每个口都能支持4K@30输入,但由于编码能力有限,不能全部做5路4K的编码,实际测试只能达到2路4K@30编码+4路1080p@30。
    在这里插入图片描述

    3. 强大的图像处理(VPSS)能力

    VPSS(Video Process Sub-System)支持对一幅输入图像进行统一预处理,如去噪、去隔行等,然后再对各通道分别进行缩放、锐化等处理,最后输出多种不同分辨率的图像。海思Hi3531D提供强大的VPSS能力。海思Hi3531D的VPSS提供了下列功能:
    DCMP(解压缩)
    CMP(压缩)
    FRC(帧率控制)
    Crop(裁剪,指VPSS 对输入图像进行裁剪)
    PreScale(预缩放,对输入图像进行水平1/2 或垂直1/2 或水平垂直1/2 的缩放)
    DEI(De-interlace,去隔行。将交错的隔行视频源还原成逐行视频源)
    NR(去噪。通过参数配置,把图像中的高斯噪声去除,使得图像变得平滑,有助于降低编码码率)
    LTI/CTI(Luma/Chroma Transition Improvement,亮度/色度过渡增强,即图像锐化即Sharpen。锐化图像的边缘和凸显图像细节,对经过缩放(Scale)后的图像进行频率补偿或增强,使得图像边缘锐利,轮廓清晰)
    Scale(缩放,对图像进行缩小或放大。VPSS 最大支持对输入图像做水平和垂直16 倍放大,或者水平和垂直15倍缩小。VPSS 放大后的输出图像宽度不能超过4096)
    ES(边缘平滑)
    IE(图像增强)
    DCI(Dynamic Contrast Improvement,动态对比度调节。对图像进行动态的对比度调节,即在增强图像暗区亮度时而不使亮区过亮,或降低亮区亮度时而不使暗区过暗)
    Cover(视频遮挡区域,对VPSS 的输出图像填充纯色块。VPSS 仅支持实心Cover,不支持虚心框Cover)
    Overlay(视频叠加区域,在GROUP 上进行位图的加载和背景色更新,支持ARGB4444、ARGB1555、ARGB8888三种格式的位图)
    Mosaic(视频马赛克区域,对VPSS 输出图像填充马赛克块)。
        板卡厂家的软件提供下面几个功能(画面融合,滚动字幕,打码,台标,去隔行等),证明了海思VPSS的强大。

    3.1 画面融合

    画面融合可以把多个视频源的画面按既定的布局拼接成另外一个画面输出,拼接的画面可以在运行状态界面上预览,也可以通过板卡的的HDMI输出接口接到电视机上监看,还可以在编码输出界面启用网络流输出。目前板卡软件预设的混合布局类型有:9宫格,4分屏,1+2,画中画。画面融合时也可以进行音频混合,在屏幕右边区域可以选择哪几个频道的声音进行混合。混合后的视音频除了通过编码压缩从网络输出以外,还可以直接把混合后的视音频从HDMI口输出,方便用户监看。题外话:这个界面还允许配置VGA输出,VGA输出可以直接把其他输入源进行输出(旁路功能)。板卡厂家提供的SDK很方便定义HMDI和VGA的输出内容,板卡厂家提供的SDK可以把HDMI和VGA输出同样的内容,也可以输出不同的内容。详细参见https://gitee.com/LinkPi/LinkLib和https://gitee.com/LinkPi/LinkLib/wikis/pages说明。
    在这里插入图片描述
        上图可以看到,9个1080P@60的画面融合成一个画面,这得多大的数据量啊,要是全部由CPU来搬运数据,就算是Intel的I7 CPU也忙不过来吧。使用cat /proc/umap/vpss来看看VPSS处理的数据量:
    在这里插入图片描述
        强大的画面融合(融屏)能力,在下面的应用中应该是可以大展身手了:

    教育录播行业,经典的融屏布局是是2+1,左边是一个大框显示老师的PPT课件,右边2个小框,一个显示学生的画面,根据上课过程中的需要,自动切换或者手动切换最重要的信息到左边的大框中。自动切换应该也不难了,配合OPENCV的一些算法可以轻松搞定的。这类应用还适合法庭庭审录播,戒毒所和监狱类的宣教系统中。
    指挥中心的大屏方案,指挥中心通常要接入很多点的监控视频,现在市面上的监控摄像头大多都是网络摄像头了,早些年大多都是TI的芯片方案,最近几乎是清一色的华为海思方案了,所以利用海思Hi3531D强大的解码能力来做大屏显示方案,应该是不错的,而且华为自家解自家芯片出来的视频流,应该说是最佳搭配了。
    切换台,导播台。该板卡有5个HDMI输入口,每个HDMI口最高都支持4K@30(3840x2160)的信号,而且还可以支持12路网络流输入(或者12个本地文件),从硬件的角度上看,满足切换台和导播台多种输入源的要求,再加上强大的VPSS处理能力,做这类产品是得心应手了。

    3.2 滚动字幕,打码(加马赛克),添加台标(LOGO)

    这几个功能很常见,监控产品都能做,据说现在监控产品的大厂例如海康和大华也都在用华为海思的芯片了,所以这几个功能不算什么黑科技了。上个图给大家看看吧:
    在这里插入图片描述

    3.3 全帧率去隔行,裁剪(裁边)

    板卡厂家软件上有个开关叫全帧率去隔行,我不大理解是什么意思,联系了板卡厂家,板卡厂家解释说他们的软件有2种去隔行方法,一个是海思自带的去隔行算法,一个是板卡厂家自己做的去隔行算法。若使用海思自带的去隔行算法,帧率就会减半,例如输入信号源是1080i@60,去隔行后帧率降为30fps即1080p@30了。若使用板卡厂家的全帧率去隔行算法,则帧率不变,例如输入信号源是1080i@60,去隔行后为1080p@60。一开始,我认为是这个厂家故弄玄虚,把海思去隔行后的数据多复制一份,这样帧率就可以维持不变了,后来我打开他们神奇的全帧率去隔行开关,录了一段动作变化很大的视频(例如游戏或者赛车足球什么的),录好以后用回放软件一帧一帧播放,发现没有相同画面的帧,这足以可以证明厂家不是故弄玄虚的,是货真价实的。由此可见海思VPSS的架构足够开放,能让开发者自行编写一些算法。有些人怀疑这些算法是跑在CPU上的,这种怀疑是多余的,人家5个输入源可以同时做全帧率去隔行,我不相信海思那么弱的ARM CPU能干这个事。
        国内由于起步比较晚,1080i的HDMI设备很少见,但在国外,大量1080i的HDMI设备还在使用,所以去隔行还真很有必要的。尤其是游戏直播,足球赛事直播,赛车直播等,这些画面变化是非常大的,所以由于隔行引起的百叶窗效果特别明显,若采用海思内置的去隔行算法,帧率减半,虽然百叶窗效果不见了,但画面流畅度就不佳,因此板卡厂家做的全帧率去隔行真是国外直播行业的及时雨。
        板卡厂家的软件还支持画面裁剪(裁边)。工程商在施工时经常看到有些信号的边缘总有各种各样的现象,有些信号的上边有一行白色的横条(例如DVD信号),有些信号的左右两侧有闪烁的绿条红条白条,这些虽然不致命,但经常被甲方以此为由拒绝通过验收,因此让这些工程商苦不堪言。有了这个裁剪(裁边)功能,就变得非常容易了,直接裁掉不要就好了,so easy!😜
    在这里插入图片描述

    4. 同时输出多种网络流协议

    海思的SDK没有提供网络流协议,也没有视频和音频的封装,就几个基于raw流的sample,sample里面各种结构体,都不知道如何填写,真让视音频开发小白们抓狂。板卡厂家提供的SDK提供了各种流协议:HTTP, HLS, RTSP, UDP, RTMP拉流和RTMP推流。而且能同时打开这些流协议,可见海思Hi3531D内置的ARM CPU也不是盖的。而且RTSP, UDP, RTMP的延迟都在1秒以内(最快的可以做到200ms以内)。有了板卡厂家的SDK,想购买h264编码开发板,h265编码开发板,海思开发板,Hi3531d开发板,Hdmi开发板的小白们,还犹豫什么?😍
    在这里插入图片描述
        该板卡支持丰富的网络流协议,支持的编码解码路数又多(支持编码的路数是12路1080p@30 H264/H265编码,支持解码的路数也是12路1080p@30 H264/H265解码)。可以适用下面的应用:

    转码应用,前几年H265还没有成熟的硬件方案,所以市面上的大多编码设备都是以H264为主。想获得同等的编码质量,H265要比H264节省25%的带宽,对于带宽成本很高的中国来说,能节省25%是非常诱人的。因此可以输入H264网络流,然后转码输出成H265网络流或者H265文件,这就是转码应用了。
    转流协议,该板卡支持不解码转流协议,例如http转rtmp,http转rtsp,http转udp,rtsp转http,rtsp转rtmp,rtsp转udp,rtmp转http,rtmp转rtsp,rtmp转udp等等。由于不用解码,所以不占海思Hi3531d的编码解码资源,只占一点点ARM CPU的资源(用于数据搬运),所以可以支持很多路的不解码转流协议。

    5. 软肋:音频编码和解码

    海思Hi3531d拥有强大的视频编码和解码能力,那对音频编码和解码那应该是小菜一碟了吧?错!错!!错!!!,也许是LICENSE的原因,音频编码和解码都不是硬件处理的,而是使用了ARM CPU去做的,那个颗弱小的嵌入式ARM CPU,处理音频的重采样(resample),处理回声消除(EC),做AAC编码和解码,都需要做很多优化,否则ARM CPU占用就爆了。对于做监控行业的人来说,也许并不是什么大事,毕竟监控行业的音频通常是单声道的,8K采样率的,16bit的采样精度,数据量少,CPU占用不明显,但对于做IPTV编码器的人来说,要掂量掂量自己的能力了,双声道,采样率48K,采样精度24bit,这数据量比监控行业大多了,而且IPTV编码器的音频音质要求比较高,弄不好产品是出不了货的。我们评测该板卡厂家的音频,倒是还不错,估计花费了不少心思的。而且他们还提供了音频软件增益(音量放大)功能,普通的编码器类产品都没有这个功能,但这个功能非常实用,有些输入源声音实在是太小了,又不可能要求用户在终端播放设备统一调整。
    在这里插入图片描述

    6. 总结: 某为是有良心的企业

    经过评测,证实了聊天群里行家说的话是真的,同时也印证了某为是有良心的企业,为了不过分刺激对手,故意隐藏了自己的真实的实力。

    7 我们的优势

    在这里插入图片描述
    最后来说说ENC2, ENC5的优势就是采用了海思Hi3531D编码芯片。希望这个编码器评测能给大家带来帮助,感谢大家辛苦的看完,记得多多支持和点赞,关注我哦!!!!

    参考链接:https://blog.csdn.net/weixin_41486034/article/details/106240240

    展开全文
  • •参照用户手册搭建开发环境、编译3531D工程、配置网络启动参数。 •将带有HDMI音视频输出功能的设备(如摄像机、笔记本、机顶盒等)接入评估板的HDMI-A接口 •上电,进入/root/demo目录 •运行Stream程序 •使用...

    Stream

    该示例程序演示了如何编码并串流成常见的直播协议。

    该示例仅包含了rtsprtmp协议,更多协议可以参考Encoder工程

    准备工作

    •参照用户手册搭建开发环境、编译3531D工程、配置网络启动参数。
    •将带有HDMI音视频输出功能的设备(如摄像机、笔记本、机顶盒等)接入评估板的HDMI-A接口
    •上电,进入/root/demo目录
    •运行Stream程序
    •使用VLC等播放器,打开直播地址rtsp://IP/testrtmp://IP/live/test

    运行结果

    在这里插入图片描述
    在这里插入图片描述

    源代码

    #include <QCoreApplication>
    #include "Link.h"
    int main(int argc, char *argv[])
    {
        QCoreApplication a(argc, argv);
        Link::init();
    
        LinkObject *ai=Link::create("InputAi");
        QVariantMap dataAi;
        dataAi["interface"]="HDMI-A";
        ai->start(dataAi);
    
        LinkObject *vi=Link::create("InputVi");
        QVariantMap dataVi;
        dataVi["interface"]="HDMI-A";
        vi->start(dataVi);
    
        LinkObject *encA=Link::create("EncodeA");
        QVariantMap dataEncA;
        dataEncA["codec"]="aac";
        dataEncA["samplerate"]=48000;
        dataEncA["bitrate"]=32;
        encA->start(dataEncA);
    
        LinkObject *encV=Link::create("EncodeV");
        QVariantMap dataEncV;
        dataEncV["codec"]="h264";
        dataEncV["width"]=1920;
        dataEncV["height"]=1080;
        dataEncV["bitrate"]=4000;
        encV->start(dataEncV);
    
        LinkObject *rtmp=Link::create("Mux");
        QVariantMap dataRtmp;
        dataRtmp["path"]="rtmp://127.0.0.1/live/test";
        rtmp->start(dataRtmp);
    
        ai->linkA(encA)->linkA(rtmp);
        vi->linkV(encV)->linkV(rtmp);
    
        LinkObject *rtspServer=Link::create("Rtsp");
        rtspServer->start();
    
        LinkObject *rtsp=Link::create("Mux");
        QVariantMap dataRtsp;
        dataRtsp["path"]="mem://test";
        dataRtsp["format"]="rtsp";
        rtsp->start(dataRtsp);
    
        encA->linkA(rtsp)->linkA(rtspServer);
        encV->linkV(rtsp)->linkV(rtspServer);
    
        return a.exec();
    }
    

    完整工程

    https://gitee.com/LinkPi/3531D/tree/master/Stream

    展开全文
  • 准备用hi3531d做hdmi输入,但是只有IT6801FN的驱动ko,担心调不好,于是决定先使用原来一直用的sii9233a,这款芯片的资料比较难找,而且都是英文的,所以我先放个链接好了 链接:...

    前言

    准备用hi3531d做hdmi输入,但是只有IT6801FN的驱动ko,担心调不好,于是决定先使用原来一直用的sii9233a,这款芯片的资料比较难找,而且都是英文的,所以我先放个链接好了

    链接:https://pan.baidu.com/s/1Ikt8G5sJTTrnsrHmg7SLUQ 提取码:gkh7

    通过海思的应用层i2c接口,完成sii9233a的配置,代码较长,可以参考,从main函数看起

    sii9233a.c

    #include "sii9233a.h"
    #define SELF_TEST 1
    
    
    int hi_i2c_read_single(SII9233_Dev_t dev, uint8_t dev_addr, uint8_t reg_addr, uint8_t *value)
    {
        int status = 0;
        char recvbuf[2] = {0};
        ioctl(dev.i2c_dev_fd, I2C_SLAVE_FORCE, dev_addr); 
        ioctl(dev.i2c_dev_fd, I2C_16BIT_REG, 0);  //8bit
        ioctl(dev.i2c_dev_fd, I2C_16BIT_DATA, 0); //8bit
        recvbuf[0] = reg_addr;
        recvbuf[1] = 0;
        status = read(dev.i2c_dev_fd, recvbuf, 1);
        *value = recvbuf[0];
        if(status <= 0)
        {
            sii9233_printf("i2c device[%s] read error, dev_addr=0x%x, reg_addr=0x%x\n", dev.i2c_dev_name, dev_addr, reg_addr);
            return -1;
        }
        sii9233_printf("i2c device[%s] read, dev_addr=0x%x, reg_addr=0x%x, value=0x%x\n", dev.i2c_dev_name, dev_addr, reg_addr, recvbuf[0]);
        return status;
    }
    
    int hi_i2c_write_single(SII9233_Dev_t dev, uint8_t dev_addr, uint8_t reg_addr, uint8_t value)
    {
        int status = 0;
        char sendbuf[2];
        ioctl(dev.i2c_dev_fd, I2C_SLAVE_FORCE, dev_addr); 
        ioctl(dev.i2c_dev_fd, I2C_16BIT_REG, 0);  //8bit
        ioctl(dev.i2c_dev_fd, I2C_16BIT_DATA, 0); //8bit
        sendbuf[0] = reg_addr;
        sendbuf[1] = value;
        status = write(dev.i2c_dev_fd, sendbuf, 2);
        if(status <= 0)
        {
            sii9233_printf("i2c device[%s] write error, dev_addr=0x%x, reg_addr=0x%x, value=0x%x\n", dev.i2c_dev_name, dev_addr, reg_addr, value);
            return -1;
        }
        sii9233_printf("i2c device[%s] write, dev_addr=0x%x, reg_addr=0x%x, value=0x%x\n", dev.i2c_dev_name, dev_addr, reg_addr, value);
        return status;
    }
    
    int hi_i2c_read(SII9233_Dev_t dev, uint8_t dev_addr, uint8_t *reg_addr, uint8_t *value, uint8_t len)
    {
        int status = 0;
        int i = 0;
        for (i=0; i < len; i++)
        {
            status = hi_i2c_read_single(dev, dev_addr, reg_addr[i], &value[i]);
            if (status <= 0) 
                return -1;
        }
        return 0;
    }
    
    int hi_i2c_write(SII9233_Dev_t dev, uint8_t dev_addr, uint8_t *reg_addr, uint8_t *value, uint16_t len)
    {
        int status = 0;
        int i = 0;
        for (i=0; i < len; i++)
        {
            status = hi_i2c_write_single(dev, dev_addr, reg_addr[i], value[i]);
            if (status <= 0) 
                return -1;
        }
        return 0;
    }
    
    
    
    int sii9233_para_init(SII9233_Dev_t *pdev)
    {
        memset(pdev, 0, sizeof(SII9233_Dev_t));
        strcpy(pdev->i2c_dev_name, "/dev/i2c-1");
        pdev->first_dev_addr = 0x62;
        pdev->second_dev_addr = 0x6a;
        pdev->xv_color_addr = 0x64;
        pdev->edid_addr = 0xe0;
        pdev->cec_addr = 0xc0;
        pdev->videoDataFormat = SYSTEM_DF_YUV422P;
        pdev->standard = SYSTEM_STD_1080P_30;
        return 0;
    }
    
    int sii9233_open(SII9233_Dev_t *pdev)
    {
        pdev->i2c_dev_fd = open(pdev->i2c_dev_name, O_RDWR);
        if(pdev->i2c_dev_fd < 0)
        {
            sii9233_printf("open i2c device[%s] error, fd = %d\n", pdev->i2c_dev_name, pdev->i2c_dev_fd);
            return pdev->i2c_dev_fd;
        }
        return 0;
    }
    
    int sii9233_close(SII9233_Dev_t *pdev)
    {
        close(pdev->i2c_dev_fd);
        return 0;
    }
    
    int sii9233_set_slave_addr_reg(SII9233_Dev_t *pdev)
    {
        // Device_sii9233aSetSlaveAddress
        // i2c_write 0x1 0x62 0x15 0x64 1 1
        // i2c_write 0x1 0x62 0x18 0xc0 1 1
        // i2c_write 0x1 0x62 0x19 0xe0 1 1
        int status = 0;
        int reg_num = 0;
    
        pdev->regaddr[0] = 0x15;
        pdev->regaddr[1] = 0x18;
        pdev->regaddr[2] = 0x19;
    
        pdev->regdata[0] = pdev->xv_color_addr;
        pdev->regdata[1] = pdev->cec_addr;
        pdev->regdata[2] = pdev->edid_addr;
    
        reg_num = 3;
    
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_slave_addr error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    int sii9233_set_factory_reg(SII9233_Dev_t *pdev)
    {
        // i2c_write 0x1 0x62 0x0e 0x40 1 1
        // i2c_write 0x1 0xe0 0xe5 0x02 1 1
        // i2c_write 0x1 0x64 0x81 0x18 1 1
        // i2c_write 0x1 0x64 0x87 0x43 1 1
        // i2c_write 0x1 0x64 0x89 0x00 1 1
        // i2c_write 0x1 0x64 0x92 0x8a 1 1
        // i2c_write 0x1 0x64 0x93 0xaa 1 1
        // i2c_write 0x1 0x64 0x94 0x1a 1 1
        // i2c_write 0x1 0x64 0x95 0x2a 1 1
        // i2c_write 0x1 0x64 0xb5 0x40 1 1
        // i2c_write 0x1 0x64 0xbb 0x04 1 1
        int status = 0;
        int reg_num = 0;
    
        pdev->regaddr[0] = 0x0e;
        pdev->regdata[0] = 0x40;
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_factory_reg error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
    
        pdev->regaddr[0] = 0xe5;
        pdev->regdata[0] = 0x2;
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_factory_reg error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
    
        pdev->regaddr[0] = 0x81;
        pdev->regaddr[1] = 0x87;
        pdev->regaddr[2] = 0x89;
        pdev->regaddr[3] = 0x92;
        pdev->regaddr[4] = 0x93;
        pdev->regaddr[5] = 0x94;
        pdev->regaddr[6] = 0x95;
        pdev->regaddr[7] = 0xb5;
        pdev->regaddr[8] = 0xbb;
    
        pdev->regdata[0] = 0x18;
        pdev->regdata[1] = 0x43;    //这个寄存器的值,读出来看是0x03,设了0x43也改变不了,但是好像没什么影响
        pdev->regdata[2] = 0x00;
        pdev->regdata[3] = 0x8a;
        pdev->regdata[4] = 0xaa;
        pdev->regdata[5] = 0x1a;
        pdev->regdata[6] = 0x2a;
        pdev->regdata[7] = 0x40;
        pdev->regdata[8] = 0x04;
    
        reg_num = 9;
    
        status = hi_i2c_write(*pdev, pdev->xv_color_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_factory_reg error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->xv_color_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    
    }
    
    int sii9233_init_edid_reg(SII9233_Dev_t *pdev)
    {
    // i2c_write 0x1 0xe0 0x1 0xf 1 1
    // i2c_write 0x1 0xe0 0x4 0x1 1 1
    // i2c_write 0x1 0xe0 0x2 0x0 1 1
    // 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x4D, 0x29, 0x23, 0x92, 0x01, 0x00, 0x00, 0x00,
    // 0x00, 0x12, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
    // 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
    // 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
    // 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
    // 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x43,
    // 0x50, 0x39, 0x32, 0x32, 0x33, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
    // 0x00, 0x17, 0x78, 0x0F, 0x7E, 0x17, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x66,
    // 0x02, 0x03, 0x3D, 0x72, 0x55, 0x90, 0x04, 0x03, 0x02, 0x0E, 0x0F, 0x07, 0x23, 0x24, 0x05, 0x94,
    // 0x13, 0x12, 0x11, 0x1D, 0x1E, 0xA0, 0xA1, 0xA2, 0x01, 0x1F, 0x35, 0x09, 0x7F, 0x07, 0x09, 0x7F,
    // 0x07, 0x17, 0x07, 0x50, 0x3F, 0x06, 0xC0, 0x57, 0x06, 0x00, 0x5F, 0x7F, 0x01, 0x67, 0x1F, 0x00,
    // 0x83, 0x4F, 0x00, 0x00, 0x68, 0x03, 0x0C, 0x00, 0x10, 0x00, 0xB8, 0x2D, 0x00, 0x8C, 0x0A, 0xD0,
    // 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x8C,
    // 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00,
    // 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC4, 0x8E, 0x21,
    // 0x00, 0x00, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E
        int status = 0 ,i;
        int reg_num = 0;
        uint8_t fifoValue;
    
        pdev->regaddr[0] = 0xd1;
        pdev->regdata[0] = 0;   
        reg_num = 1;
    // i2c_read form i2c-1 devaddr:0xe0 regaddr:0xd1 value:0x1
        status = hi_i2c_read(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_port_switch error\n");
            return -1;
        }
    
        if(pdev->regdata[0] == 0x01)
    		fifoValue =0x01;
        else if((pdev->regdata[0] == 0x02) || (pdev->regdata[0] == 0x03))
    		fifoValue =0x02;
        else if((pdev->regdata[0] == 0x04) || (pdev->regdata[0] == 0x05))
    		fifoValue =0x04;
        else if((pdev->regdata[0] == 0x08) || (pdev->regdata[0] == 0x09))
    		fifoValue =0x08;
        else
    		fifoValue =0x02;
    
        pdev->regaddr[0] = 0x01;
        pdev->regaddr[1] = 0x04;
        pdev->regaddr[2] = 0x02;
    
        pdev->regdata[0] = 0x0f;
        pdev->regdata[1] = fifoValue;
        pdev->regdata[2] = 0x00;
    
        reg_num = 3;
    
        status = hi_i2c_write(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_init_edid_reg error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
    
        uint8_t buf[0x100] = {
            0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x4D, 0x29, 0x23, 0x92, 0x01, 0x00, 0x00, 0x00,
            0x00, 0x12, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
            0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
            0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
            0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
            0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x43,
            0x50, 0x39, 0x32, 0x32, 0x33, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
            0x00, 0x17, 0x78, 0x0F, 0x7E, 0x17, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x66,
            0x02, 0x03, 0x3D, 0x72, 0x55, 0x90, 0x04, 0x03, 0x02, 0x0E, 0x0F, 0x07, 0x23, 0x24, 0x05, 0x94,
            0x13, 0x12, 0x11, 0x1D, 0x1E, 0xA0, 0xA1, 0xA2, 0x01, 0x1F, 0x35, 0x09, 0x7F, 0x07, 0x09, 0x7F,
            0x07, 0x17, 0x07, 0x50, 0x3F, 0x06, 0xC0, 0x57, 0x06, 0x00, 0x5F, 0x7F, 0x01, 0x67, 0x1F, 0x00,
            0x83, 0x4F, 0x00, 0x00, 0x68, 0x03, 0x0C, 0x00, 0x10, 0x00, 0xB8, 0x2D, 0x00, 0x8C, 0x0A, 0xD0,
            0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x8C,
            0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00,
            0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC4, 0x8E, 0x21,
            0x00, 0x00, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E,
        };
        for (i = 0; i < 0x100; i++)
        {
            pdev->regaddr[i] = 0x03;
            pdev->regdata[i] = buf[i];
        }
        status = hi_i2c_write(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, 0x100);
        if(status < 0)
        {
            sii9233_printf("sii9233_init_edid_reg error\n");
            return -1;
        }
    
        return 0;
    }
    
    int sii9233_get_chip_id(SII9233_Dev_t *pdev)
    {
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x0 value:0x1
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x1 value:0x0
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x2 value:0x33
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x3 value:0x92
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x4 value:0x33
    // get chip id : chipId=0x9233, chipRevision=0x33, firmwareVersion=0x1
        int status = 0;
        int reg_num = 0;
        pdev->regaddr[0] = 0x00;
        pdev->regaddr[1] = 0x01;
        pdev->regaddr[2] = 0x02;
        pdev->regaddr[3] = 0x03;
        pdev->regaddr[4] = 0x04;
    
        pdev->regdata[0] = 0;
        pdev->regdata[1] = 0;
        pdev->regdata[2] = 0;
        pdev->regdata[3] = 0;
        pdev->regdata[4] = 0;
    
        reg_num = 5;
    
        status = hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_get_chip_id error\n");
            return -1;
        }
    
        pdev->chip_info.chipId = pdev->regdata[3] << 8 | pdev->regdata[2];
        pdev->chip_info.chipRevision = (pdev->regdata[4]);
        pdev->chip_info.firmwareVersion = (pdev->regdata[1] << 8 | pdev->regdata[0]);
        // sii9233_printf("sii9233_get_chip_id : chipId=0x%x, chipRevision=0x%x, firmwareVersion=0x%x\n", \
        //     pdev->chip_info.chipId, pdev->chip_info.chipRevision, pdev->chip_info.firmwareVersion);
        return 0;
    }
    
    int sii9233_get_video_status(SII9233_Dev_t *pdev)
    {
    // i2c_write 0x1 0x62 0x6a 0x0 1 1
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x3a value:0x98
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x3b value:0x8
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x3c value:0x65
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x3d value:0x4
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x4e value:0x80
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x4f value:0x7
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x50 value:0x38
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x51 value:0x4
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x6e value:0xe8
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x6f value:0x2
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x55 value:0x3
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x6 value:0x3b
    // hRes=0x898, vRes=0x465, dePix=0x780, deLin=0x438, xclkInPclk=0x2e8, vidStat=0x3, sysStat=0x3b
    // i2c_write 0x1 0x62 0x6a 0x1 1 1
    //  VCAP: DEVICE-0 (0x31): Detected video (1920x1080@32625Hz, 0) !!!
        int status = 0;
        int reg_num = 0;
    
        uint32_t hRes = 0;          //horizontal resolution
        uint32_t vRes = 0;          //vertical resolution
        uint32_t dePix = 0;         //horizontal active data resolution
        uint32_t deLin = 0;         //vertical active data resolution
        uint32_t xclkInPclk = 0;    //number of xclks per 2048 video clocks
        uint32_t vidStat = 0;       //video status
        uint32_t sysStat = 0;       //system status
    
        pdev->regaddr[0] = 0x6a;
        pdev->regdata[0] = 0x00;
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_get_video_status error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
    
        pdev->regaddr[0] = 0x3a;
        pdev->regaddr[1] = 0x3b;
        pdev->regaddr[2] = 0x3c;
        pdev->regaddr[3] = 0x3d;
        pdev->regaddr[4] = 0x4e;
        pdev->regaddr[5] = 0x4f;
        pdev->regaddr[6] = 0x50;
        pdev->regaddr[7] = 0x51;
        pdev->regaddr[8] = 0x6e;
        pdev->regaddr[9] = 0x6f;
        pdev->regaddr[10] = 0x55;
        pdev->regaddr[11] = 0x06;
    
        pdev->regdata[0] = 0x0;
        pdev->regdata[1] = 0x0;
        pdev->regdata[2] = 0x0;
        pdev->regdata[3] = 0x0;
        pdev->regdata[4] = 0x0;
        pdev->regdata[5] = 0x0;
        pdev->regdata[6] = 0x0;
        pdev->regdata[7] = 0x0;
        pdev->regdata[8] = 0x0;
        pdev->regdata[9] = 0x0;
        pdev->regdata[10] =0x0;
        pdev->regdata[11] =0x0;
    
        reg_num = 12;
    
        status = hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_get_video_status error\n");
            return -1;
        }
    
        hRes = ((uint32_t)pdev->regdata[1] << 8) | pdev->regdata[0];
        vRes = ( ( uint32_t ) pdev->regdata[3] << 8 ) | pdev->regdata[2];
        dePix = ( ( uint32_t ) pdev->regdata[5] << 8 ) | pdev->regdata[4];
        deLin = ( ( uint32_t ) pdev->regdata[7] << 8 ) | pdev->regdata[6];
        xclkInPclk = ( ( uint32_t ) pdev->regdata[9] << 8 ) | pdev->regdata[8];
        vidStat = pdev->regdata[10];
        sysStat = pdev->regdata[11];
    
        // sii9233_printf("hRes=0x%x, vRes=0x%x, dePix=0x%x, deLin=0x%x, xclkInPclk=0x%x, vidStat=0x%x, sysStat=0x%x\n", hRes, vRes, dePix, deLin, xclkInPclk, vidStat, sysStat);
    
        if ( sysStat & DEVICE_SII9233A_VID_DETECT )
        {
            uint32_t t_line;
            pdev->video_status.isVideoDetect = true;
    
            if ( vidStat & DEVICE_SII9233A_VID_INTERLACE )
            {
                 pdev->video_status.isInterlaced = true;
            }
    
            pdev->video_status.frameWidth = dePix;
            pdev->video_status.frameHeight = deLin;
    
            //time interval in usecs for each line
            t_line = ( uint32_t ) ( ( ( uint32_t ) hRes * xclkInPclk * 1000 ) / ( DEVICE_SII9233A_FXTAL_KHZ * 2048 ) ); /* in usecs */
            //time interval in usecs for each frame/field
            pdev->video_status.frameInterval = t_line * vRes;   
        }
    
        pdev->regaddr[0] = 0x6A;
        pdev->regdata[0] = 0x01;
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_get_video_status error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    int sii9233_output_enable(SII9233_Dev_t *pdev, bool enable)
    {
        int status = 0;
        int reg_num = 0;
    
        pdev->regaddr[0] = 0x3E;
        pdev->regdata[0] = 0xC3;
        if ( enable )
            pdev->regdata[0] |= ( 1 << 2 );
    
        pdev->regaddr[1] = 0x3F;
        pdev->regdata[1] = 0xAD;
        if ( enable )
            pdev->regdata[1] |= ( 1 << 6 );
     
    
        reg_num = 2;
        status = hi_i2c_write(*pdev, pdev->second_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_output_enable error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->second_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    
    int sii9233_start(SII9233_Dev_t *pdev)
    {
        int status = 0;
        status = sii9233_output_enable(pdev, true);
        if(status < 0)
        {
            sii9233_printf("sii9233_stop error\n");
            return -1;
        }
        return 0;
    }
    
    int sii9233_stop(SII9233_Dev_t *pdev)
    {
    // Device_sii9233aStop
        // Device_sii9233aOutputEnable(pObj,false);
        // i2c_write 0x1 0x6a 0x3e 0xc3 1 1
        // i2c_write 0x1 0x6a 0x3f 0xad 1 1
        int status = 0;
        status = sii9233_output_enable(pdev, false);
        if(status < 0)
        {
            sii9233_printf("sii9233_stop error\n");
            return -1;
        }
        return 0;
    }
    
    
    int sii9233_powerdown(SII9233_Dev_t *pdev, bool powerdown) 
    {
        int status = 0;
        int reg_num = 0;
    
        pdev->regaddr[0] = 0x08;
        pdev->regdata[0] = 0;
        reg_num = 1;
        status = hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_powerdown error\n");
            return -1;
        }
    
        if ( powerdown )
            pdev->regdata[0] &= 0xfd;  // power down  
        else
            pdev->regdata[0] |= 0x01;  // normal operation 
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_powerdown error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    
    int sii9233_select_tmds_core(SII9233_Dev_t *pdev, uint32_t coreId)
    {
    // i2c_write 0x1 0x62 0x9 0x10 1 1
    // i2c_write 0x1 0x62 0xa 0x8 1 1
    // i2c_write 0x1 0x62 0x10 0x1 1 1
        int status = 0;
        int reg_num = 0;
        // sii9233_printf("select_port = %d \n",coreId+1);
        pdev->regaddr[0] = 0x09;
        pdev->regaddr[1] = 0x0A;
        pdev->regaddr[2] = 0x10;
    
        pdev->regdata[0] =(0x01 << coreId) << 4;     // DDC0_EN = 1
        pdev->regdata[1] = 0x08 | coreId;            // DDCDLY_EN = 1, HDMI_PORT0
        pdev->regdata[2] = 0x01 << (2 * coreId);     // HPD0 = 1
    
        reg_num = 3;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_powerdown error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    
    
    int sii9233_port_switch(SII9233_Dev_t *pdev)
    {
        int status = 0;
        int reg_num = 0;
        pdev->regaddr[0] = 0xd1;
        pdev->regdata[0] = 0;   
        reg_num = 1;
    // i2c_read form i2c-1 devaddr:0xe0 regaddr:0xd1 value:0x1
        status = hi_i2c_read(*pdev, pdev->edid_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_port_switch error\n");
            return -1;
        }
    
        if(pdev->regdata[0] == 1)
    		status = sii9233_select_tmds_core(pdev,0);
        else if( (pdev->regdata[0] == 2) || (pdev->regdata[0] == 3))
    		status = sii9233_select_tmds_core(pdev,1);
        else if( (pdev->regdata[0] == 4) || (pdev->regdata[0] == 5))
    		status = sii9233_select_tmds_core(pdev,2);
        else if( (pdev->regdata[0] == 8)|| (pdev->regdata[0] == 9))
    		status = sii9233_select_tmds_core(pdev,3);
        else
    		status = sii9233_select_tmds_core(pdev,1);
    
        return 0;
    }
    
    int sii9233_reset(SII9233_Dev_t *pdev)
    {
        //Device_sii9233aStop
        //Device_sii9233aPowerDown
    
        int status = 0;
        int reg_num = 0;
    
        status = sii9233_stop(pdev);                //disable outputs
        if(status < 0)
        {
            sii9233_printf("sii9233_reset error\n");
            return -1;
        }
    
    // i2c_read form i2c-1 devaddr:0x62 regaddr:0x8 value:0x5
    // i2c_write 0x1 0x62 0x8 0x5 1 1
        status = sii9233_powerdown(pdev, false);    //Normal operation
        if(status < 0)
        {
            sii9233_printf("sii9233_reset error\n");
            return -1;
        }
    
    // i2c_write 0x1 0x62 0x5 0x2f 1 1
    // i2c_write 0x1 0x62 0x7 0x9 1 1
        pdev->regaddr[0] = 0x05;
        pdev->regaddr[1] = 0x07;
    
        pdev->regdata[0] = 0x2F;    // reset AAC, HDCP, ACR, audio FIFO, SW
        pdev->regdata[1] = 0x09;    // reset HDCP 
    
        reg_num = 2;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_reset error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        
        usleep( 50000 );            //wait for reset to be effective
    
    // i2c_write 0x1 0x62 0x5 0x10 1 1
        //remove reset and setup in auto-reset mode
        pdev->regaddr[0] = 0x05;
        pdev->regdata[0] = 0x10;    //auto-reset SW
        reg_num = 1;
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_reset error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
    
        //select TDMS core
        sii9233_port_switch(pdev);
    // i2c_write 0x1 0x62 0x2e 0xe0 1 1
        pdev->regaddr[0] = 0x2E;
        pdev->regdata[0] = 0xE0;    //set HDCP
        reg_num = 1;
    
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_reset error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    int sii9233_detect_video(SII9233_Dev_t *pdev)
    {
        int status = 0;
        usleep(100000);
        status = sii9233_get_video_status(pdev);
        if ( status < 0)
            return status;
    
        if( pdev->video_status.isVideoDetect != true )
        {
            printf("NO Video Detected, get video info failed !!!\n");
            return -1;
        }
    
        status = sii9233_read_av_info(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_video_mode error\n");
            return -1;
        }
        return 0;
    }
    
    int sii9233_read_av_info(SII9233_Dev_t *pdev)
    {
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x40 value:0x82
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x41 value:0x2
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x42 value:0xd
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x43 value:0x23
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x44 value:0x2
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x45 value:0x28
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x46 value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x47 value:0x22
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x48 value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x49 value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4a value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4b value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4c value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4d value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4e value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x4f value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x50 value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x51 value:0x0
    // i2c_read form i2c-1 devaddr:0x6a regaddr:0x52 value:0x0
    
        int status = 0;
        int reg_num = 0;
        uint8_t *aviData;
        uint8_t aviAddr;
        pdev->av_info.detected = false;
    
        for ( aviAddr = DEVICE_SII9233A_REG_AVI_TYPE;
              aviAddr <= DEVICE_SII9233A_REG_AVI_DBYTE15; aviAddr++ )
        {
            pdev->regaddr[reg_num] = aviAddr;
            pdev->regdata[reg_num] = 0;
            reg_num++;
        }
        status = hi_i2c_read(*pdev, pdev->second_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_port_switch error\n");
            return -1;
        }
        if ( pdev->regdata[0] == DEVICE_SII9233A_AVI_INFO_PACKET_CODE
             && pdev->regdata[1] == DEVICE_SII9233A_AVI_INFO_VERSION_CODE
             && pdev->regdata[2] == DEVICE_SII9233A_AVI_INFO_PACKET_LENGTH )
        {
            pdev->av_info.detected = true;  //Valid AVI packet recevied
            aviData = &pdev->regdata[3];    // point to start of AVI data checksum
            pdev->av_info.colorSpace = ( ( aviData[1] >> 5 ) & 0x3 );       //parse information
            pdev->av_info.colorImetric = ( ( aviData[2] >> 6 ) & 0x3 );
            pdev->av_info.pixelRepeat = ( ( aviData[5] >> 0 ) & 0xF );
    
            // sii9233_printf("av_info : colorSpace=0x%x, colorImetric=0x%x, pixelRepeat=0x%x\n",pdev->av_info.colorSpace, pdev->av_info.colorImetric, pdev->av_info.pixelRepeat);
        }
        return 0;
    }
    
    /*
      For SII9233A below parameters in Device_VideoDecoderVideoModeParams are ignored
      and any value set by user for these parameters is not effective.
    
      videoIfMode
      standard
      videoCaptureMode
      videoSystem
    
      Depending on video data format SII9233A is configured as below
    
      videoDataFormat =
       SYSTEM_DF_YUV422P   : 16-bit YUV422 single CH embedded sync auto-detect mode
       SYSTEM_DF_YUV444P   : 24-bit YUV444 single CH discrete sync auto-detect mode
       SYSTEM_DF_RGB24_888 : 24-bit RGB24  single CH discrete sync auto-detect mode
    */
    int sii9233_setup_video(SII9233_Dev_t *pdev)
    {
        int status = 0;
        int reg_num = 0;
    
        uint32_t outColorSpace, inPixRep, isBT709, cscR2Y, cscY2R, upSmp, downSmp, chMap, insSavEav;
    
        if(pdev->videoDataFormat == SYSTEM_DF_RGB24_888)
            outColorSpace = DEVICE_SII9233A_COLOR_FORMAT_RGB;
        else
            outColorSpace = DEVICE_SII9233A_COLOR_FORMAT_YUV;
    
        // Hard code AVI frame info
        if (pdev->av_info.detected == false)
        {
        	pdev->av_info.colorSpace = DEVICE_SII9233A_AVI_INFO_COLOR_RGB444;
        	pdev->av_info.colorImetric = DEVICE_SII9233A_AVI_INFO_CMETRIC_ITU709;
        	pdev->av_info.pixelRepeat = DEVICE_SII9233A_AVI_INFO_PIXREP_NONE;
    
            if ( pdev->standard==SYSTEM_STD_480I
              || pdev->standard==SYSTEM_STD_576I
              || pdev->standard==SYSTEM_STD_D1
              || pdev->standard==SYSTEM_STD_NTSC
              || pdev->standard==SYSTEM_STD_PAL )
            {
                pdev->av_info.colorImetric = DEVICE_SII9233A_AVI_INFO_CMETRIC_ITU601;
                pdev->av_info.pixelRepeat = DEVICE_SII9233A_AVI_INFO_PIXREP_2X;
            }
        }
    
    
        inPixRep = pdev->av_info.pixelRepeat;
        if ( inPixRep > DEVICE_SII9233A_AVI_INFO_PIXREP_4X )
        {
            inPixRep = 0;
            status = -1;
        }
    
        isBT709 = 1;
        if ( pdev->av_info.colorImetric == DEVICE_SII9233A_AVI_INFO_CMETRIC_ITU601 )
            isBT709 = 0;
    
        cscR2Y = 0;
        upSmp = 0;
        downSmp = 0;
        cscY2R = 0;
        insSavEav = 0;
    
        switch ( pdev->av_info.colorSpace )
        {
            case DEVICE_SII9233A_AVI_INFO_COLOR_RGB444:
                switch ( pdev->videoDataFormat )
                {
                    case SYSTEM_DF_YUV422P:
                        cscR2Y = 1;
                        downSmp = 1;
                        insSavEav = 1;
                        break;
    
                    case SYSTEM_DF_YUV444P:
                        cscR2Y = 1;
                        break;
    
                    case SYSTEM_DF_RGB24_888:
                        break;
    
                    default:
                        status = -1;
                        break;
                }
                break;
            case DEVICE_SII9233A_AVI_INFO_COLOR_YUV444:
                switch ( pdev->videoDataFormat )
                {
                    case SYSTEM_DF_YUV422P:
                        downSmp = 1;
                        insSavEav = 1;
                        break;
    
                    case SYSTEM_DF_YUV444P:
                        break;
    
                    case SYSTEM_DF_RGB24_888:
                        cscY2R = 1;
                        break;
    
                    default:
                        status = -1;
                        break;
                }
                break;
    
            case DEVICE_SII9233A_AVI_INFO_COLOR_YUV422:
                switch ( pdev->videoDataFormat )
                {
                    case SYSTEM_DF_YUV422P:
                        insSavEav = 1;
                        break;
    
                    case SYSTEM_DF_YUV444P:
                        upSmp = 1;
                        break;
    
                    case SYSTEM_DF_RGB24_888:
                        upSmp = 1;
                        cscY2R = 1;
                        break;
    
                    default:
                        status = -1;
                        break;
                }
                break;
    
            default:
                status = -1;
                break;
        }
    
    
        pdev->regaddr[0] = DEVICE_SII9233A_REG_VID_MODE_1;
        pdev->regdata[0] = ( insSavEav << 7 )  /* 1: SAV2EAV enable   , 0: disable */
            | ( 0 << 6 )    /* 1: Mux Y/C          , 0: No MUX  */
            | ( 1 << 5 )    /* 1: Dither enable    , 0: disable */
            | ( 1 << 4 )    /* 1: R2Y compress     , 0: bypass  */
            | ( cscR2Y << 3 )   /* 1: Enable R2Y CSC   , 0: bypass  */
            | ( upSmp << 2 )    /* 1: YUV422 to YUV444 , 0: bypass  */
            | ( downSmp << 1 )  /* 1: YUV444 to YUV422 , 0: bypass  */
            ;
    
        pdev->regaddr[1] = DEVICE_SII9233A_REG_VID_MODE_2;
        pdev->regdata[1] = ( 0 << 6 )  /* 0: Dither to 8bits, 1: 10bits, 2: 12bits  */
            | ( 0 << 5 )    /* 0: EVNODD LOW if field 0 is even, 1: HIGH */
            | ( 0 << 3 )    /* 1: Y2R compress     , 0: bypass , modify by ltz 20161027, adjust color difference, last value is 1 */
            | ( cscY2R << 2 )   /* 1: Y2R CSC          , 0: bypass           */
            | ( outColorSpace << 1 )    /* 0: Output format RGB, 1: YUV           */
            | ( 0 << 0 )    /* 1: Range clip enable, 0: disable          */
            ;
    
        pdev->regaddr[2] = DEVICE_SII9233A_REG_VID_CTRL;
        pdev->regdata[2] = ( 0 << 7 )  /* 0: Do not invert VSYNC, 1: invert */
            | ( 0 << 6 )    /* 0: Do not invert HSYNC, 1: invert */
            | ( isBT709 << 2 )  /* 0: Y2R BT601          , 1: BT709  */
            | ( 0 << 1 )    /* 0: 8bits RGB or YUV   , 1: YUV422 > 8 bits */
            | ( isBT709 << 0 )  /* 0: R2Y BT601          , 1: BT709  */
            ;
     
        pdev->regaddr[3] = DEVICE_SII9233A_REG_SYS_CTRL_1;
        pdev->regdata[3] = ( inPixRep << 6 )  /* 0: Output pixel clock divided 1x, 1: 1/2x, 3: 1/4x */
            | ( inPixRep << 4 ) /* 0: Input pixel replicate 1x, 1:2x, 3:4x            */
            | ( 1 << 2 )    /* 0: 12-bit mode         , 1: 24-bit mode      */
            | ( 0 << 1 )    /* 0: Normal output clock , 1: Invert clock     */
            | ( 1 << 0 )    /* 0: Power down          , 1: Normal operation */
            ;
        
        /* this is device connected to VIP1 and is connected in
           16-bit mode */
        chMap = 0x00;
    
        /*     Q[23:16]  Q[15:8]  Q[7:0]
            0:     R        G       B
            1:     R        B       G
            2:     G        R       B
            3:     G        B       R
            4:     B        R       G
            5:     B        G       R
        */
        pdev->regaddr[4] = DEVICE_SII9233A_REG_VID_CH_MAP;
        pdev->regdata[4] = chMap;
    
        reg_num = 5;
    
        status = hi_i2c_write(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
        if(status < 0)
        {
            sii9233_printf("sii9233_setup_video error\n");
            return -1;
        }
    #if SII9233_DEBUG
        hi_i2c_read(*pdev, pdev->first_dev_addr, pdev->regaddr, pdev->regdata, reg_num);
    #endif
        return 0;
    }
    
    int sii9233_set_video_mode(SII9233_Dev_t *pdev)
    {
    // Device_sii9233aReset
    // Device_sii9233aDetectVideo
        int status = 0;
        status = sii9233_reset(pdev);           //reset device
        if(status < 0)
        {
            sii9233_printf("sii9233_set_video_mode error\n");
            return -1;
        }
    
        status = sii9233_detect_video(pdev);    //detect video source properties
        if(status < 0)
        {
            sii9233_printf("sii9233_set_video_mode error\n");
            return -1;
        }
        
        status = sii9233_setup_video(pdev);    //setup video processing path based on detected source
        if(status < 0)
        {
            sii9233_printf("sii9233_set_video_mode error\n");
            return -1;
        }
        return 0;
    }
    
    int sii9233_api_init(SII9233_Dev_t *pdev)
    {
        int status = 0;
        
        status = sii9233_para_init(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_para_init error\n");
            return -1;
        }
    
        status = sii9233_open(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_open error\n");
            return -1;
        }
    
        status = sii9233_set_slave_addr_reg(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_slave_addr_reg error\n");
            return -1;
        }
    
        status = sii9233_set_factory_reg(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_factory_reg error\n");
            return -1;
        }
    
        status = sii9233_init_edid_reg(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_init_edid_reg error\n");
            return -1;
        }
    
        status = sii9233_get_chip_id(pdev);
        if(0 == status)
        {
            sii9233_get_video_status(pdev);
            if (pdev->video_status.isVideoDetect)
            {
                printf("Detected video (%dx%d@%dHz, Interlaced ? :%d) !!!\n",
                            pdev->video_status.frameWidth,
                            pdev->video_status.frameHeight,
                            pdev->video_status.frameInterval/1000,
                            pdev->video_status.isInterlaced);
    
                /* Assumption here is height width of video remains same across channels */
                if (pdev->video_status.frameHeight == 288)
                    pdev->isPalMode = true;
            }
            else
            {
                printf("sii9233_get_video_status error, NO Video Detected !!!\n");
                return -1;
            }
        }
        else {
            printf("sii9233_get_chip_id error, sii9233 Device not found !!!\n");
            return -1;
        }
    
        status = sii9233_set_video_mode(pdev);
        if(status < 0)
        {
            sii9233_printf("sii9233_set_video_mode error\n");
            return -1;
        }
    
        return 0;
    }
    int sii9233_api_deinit(SII9233_Dev_t *pdev)
    {
        return (sii9233_close(pdev));
    }
    int sii9233_api_start(SII9233_Dev_t *pdev)
    {
        return (sii9233_start(pdev));
    }
    int sii9233_api_stop(SII9233_Dev_t *pdev)
    {
        return(sii9233_stop(pdev));
    }
    
    
    
    
    
    #if SELF_TEST
    int main()
    {
        int status = 0;
        SII9233_Dev_t sii9233_dev;
    
        status = sii9233_api_init(&sii9233_dev);
        if(status < 0)
        {
            sii9233_printf("sii9233_api_init error\n");
            return -1;
        }
        printf("init done!\n");
    
        status = sii9233_api_start(&sii9233_dev);
        if(status < 0)
        {
            sii9233_printf("sii9233_api_start error\n");
            return -1;
        }
        printf("start done!\n");
        // while(1);
    
        sleep(20);
        status = sii9233_api_stop(&sii9233_dev);
        if(status < 0)
        {
            sii9233_printf("sii9233_api_stop error\n");
            return -1;
        }
        printf("stop done!\n");
    
        sleep(5);
        status = sii9233_api_deinit(&sii9233_dev);
        if(status < 0)
        {
            sii9233_printf("sii9233_api_deinit error\n");
            return -1;
        }
        printf("deinit done!\n");
        return 0;
    }
    #endif
    

    sii9233a.h

    #ifndef __SII_9233A_H__
    #define __SII_9233A_H__
    
    #include <stdio.h>
    #include <stdbool.h>
    #include <string.h>
    #include <strings.h>
    #include <fcntl.h>
    #include <sys/types.h>
    #include <sys/stat.h>
    
    inline int sii9233_printf(const char *__format, ...){};
    
    #define SII9233_DEBUG 1
    #if SII9233_DEBUG
        #define sii9233_printf printf
    #else
        #define sii9233_printf
    #endif
    
    
    #define I2C_SLAVE	    0x0703	/* Use this slave address */
    #define I2C_SLAVE_FORCE	0x0706	/* Use this slave address, even if it is already in use by a driver! */
    #define I2C_16BIT_REG   0x0709  /* 16BIT REG WIDTH */
    #define I2C_16BIT_DATA  0x070a  /* 16BIT DATA WIDTH */
    
    /* PCLK stable, Clock detect, Sync Detect */
    #define DEVICE_SII9233A_VID_DETECT          ((1<<0) | (1<<1) | (1<<4))
    
    /* Video interlace status */
    #define DEVICE_SII9233A_VID_INTERLACE       (1<<2)
    
    /* color format */
    #define DEVICE_SII9233A_COLOR_FORMAT_RGB    (0)
    #define DEVICE_SII9233A_COLOR_FORMAT_YUV    (1)
    
    /* F_xtal frequency in Khz  */
    #define DEVICE_SII9233A_FXTAL_KHZ           (27000)
    
    #define DEVICE_SII9233A_REG_AVI_TYPE        (0x40)
    #define DEVICE_SII9233A_REG_AVI_DBYTE15     (0x52)
    
    /* AVI packet info values */
    #define DEVICE_SII9233A_AVI_INFO_PACKET_CODE        (0x82)
    #define DEVICE_SII9233A_AVI_INFO_VERSION_CODE       (0x02)
    #define DEVICE_SII9233A_AVI_INFO_PACKET_LENGTH      (0x0D)
    
    /* color space  */
    #define DEVICE_SII9233A_AVI_INFO_COLOR_RGB444       (0)
    #define DEVICE_SII9233A_AVI_INFO_COLOR_YUV422       (1)
    #define DEVICE_SII9233A_AVI_INFO_COLOR_YUV444       (2)
    
    /* color imetric  */
    #define DEVICE_SII9233A_AVI_INFO_CMETRIC_NO_DATA    (0)
    #define DEVICE_SII9233A_AVI_INFO_CMETRIC_ITU601     (1)
    #define DEVICE_SII9233A_AVI_INFO_CMETRIC_ITU709     (2)
    
    /* pixel repition */
    #define DEVICE_SII9233A_AVI_INFO_PIXREP_NONE        (0)
    #define DEVICE_SII9233A_AVI_INFO_PIXREP_2X          (1)
    #define DEVICE_SII9233A_AVI_INFO_PIXREP_4X          (3)
    
    /* AVI packet info values */
    #define DEVICE_SII9233A_AVI_INFO_PACKET_CODE        (0x82)
    #define DEVICE_SII9233A_AVI_INFO_VERSION_CODE       (0x02)
    #define DEVICE_SII9233A_AVI_INFO_PACKET_LENGTH      (0x0D)
    
    
    /* SII9233A Registers - I2C Port 0 */
    #define DEVICE_SII9233A_REG_VND_IDL         (0x00)
    #define DEVICE_SII9233A_REG_VND_IDH         (0x01)
    #define DEVICE_SII9233A_REG_DEV_IDL         (0x02)
    #define DEVICE_SII9233A_REG_DEV_IDH         (0x03)
    #define DEVICE_SII9233A_REG_DEV_REV         (0x04)
    #define DEVICE_SII9233A_REG_SW_RST_0        (0x05)
    #define DEVICE_SII9233A_REG_STATE           (0x06)
    #define DEVICE_SII9233A_REG_SW_RST_1        (0x07)
    #define DEVICE_SII9233A_REG_SYS_CTRL_1      (0x08)
    #define DEVICE_SII9233A_REG_SYS_SWTCHC      (0x09)
    #define DEVICE_SII9233A_REG_HP_CTRL         (0x10)
    #define DEVICE_SII9233A_REG_SLAVE_ADDRESS_4 (0x15)
    #define DEVICE_SII9233A_REG_SLAVE_ADDRESS_2 (0x18)
    #define DEVICE_SII9233A_REG_SLAVE_ADDRESS_3 (0x19)
    #define DEVICE_SII9233A_REG_SYS_SWTCHC2     (0x0A)
    #define DEVICE_SII9233A_REG_CHIP_SEL        (0x0C)
    #define DEVICE_SII9233A_REG_HDCP_BCAPS_SET  (0x2E)
    #define DEVICE_SII9233A_REG_H_RESL          (0x3A)
    #define DEVICE_SII9233A_REG_H_RESH          (0x3B)
    #define DEVICE_SII9233A_REG_V_RESL          (0x3C)
    #define DEVICE_SII9233A_REG_V_RESH          (0x3D)
    #define DEVICE_SII9233A_REG_VID_CTRL        (0x48)
    #define DEVICE_SII9233A_REG_VID_MODE_2      (0x49)
    #define DEVICE_SII9233A_REG_VID_MODE_1      (0x4A)
    #define DEVICE_SII9233A_REG_VID_BLANK1      (0x4B)
    #define DEVICE_SII9233A_REG_VID_BLANK2      (0x4C)
    #define DEVICE_SII9233A_REG_VID_BLANK3      (0x4D)
    #define DEVICE_SII9233A_REG_DE_PIXL         (0x4E)
    #define DEVICE_SII9233A_REG_DE_PIXH         (0x4F)
    #define DEVICE_SII9233A_REG_DE_LINL         (0x50)
    #define DEVICE_SII9233A_REG_DE_LINH         (0x51)
    #define DEVICE_SII9233A_REG_VID_STAT        (0x55)
    #define DEVICE_SII9233A_REG_VID_CH_MAP      (0x56)
    #define DEVICE_SII9233A_REG_VID_AOF         (0x5F)
    #define DEVICE_SII9233A_REG_VID_XPM_EN      (0x6A)
    #define DEVICE_SII9233A_REG_VID_XPCNTL      (0x6E)
    #define DEVICE_SII9233A_REG_VID_XPCNTH      (0x6F)
    #define DEVICE_SII9233A_REG_AEC0_CTRL       (0xB5)
    #define DEVICE_SII9233A_REG_DS_BSTAT2       (0xD6)
    
    
    typedef enum
    {
        SYSTEM_DF_YUV422I_UYVY = 0x0000,
        /**< YUV 422 Interleaved format - UYVY. */
        SYSTEM_DF_YUV422I_YUYV,
        /**< YUV 422 Interleaved format - YUYV. */
        SYSTEM_DF_YUV422I_YVYU,
        /**< YUV 422 Interleaved format - YVYU. */
        SYSTEM_DF_YUV422I_VYUY,
        /**< YUV 422 Interleaved format - VYUY. */
        SYSTEM_DF_YUV422SP_UV,
        /**< YUV 422 Semi-Planar - Y separate, UV interleaved. */
        SYSTEM_DF_YUV422SP_VU,
        /**< YUV 422 Semi-Planar - Y separate, VU interleaved. */
        SYSTEM_DF_YUV422P,
        /**< YUV 422 Planar - Y, U and V separate. */
        SYSTEM_DF_YUV420SP_UV,
        /**< YUV 420 Semi-Planar - Y separate, UV interleaved. */
        SYSTEM_DF_YUV420SP_VU,
        /**< YUV 420 Semi-Planar - Y separate, VU interleaved. */
        SYSTEM_DF_YUV420P,
        /**< YUV 420 Planar - Y, U and V separate. */
        SYSTEM_DF_YUV444P,
        /**< YUV 444 Planar - Y, U and V separate. */
        SYSTEM_DF_YUV444I,
        /**< YUV 444 interleaved - YUVYUV... */
        SYSTEM_DF_RGB16_565 = 0x1000,
        /**< RGB565 16-bit - 5-bits R, 6-bits G, 5-bits B. */
        SYSTEM_DF_ARGB16_1555,
        /**< ARGB1555 16-bit - 5-bits R, 5-bits G, 5-bits B, 1-bit Alpha (MSB). */
        SYSTEM_DF_RGBA16_5551,
        /**< RGBA5551 16-bit - 5-bits R, 5-bits G, 5-bits B, 1-bit Alpha (LSB). */
        SYSTEM_DF_ARGB16_4444,
        /**< ARGB4444 16-bit - 4-bits R, 4-bits G, 4-bits B, 4-bit Alpha (MSB). */
        SYSTEM_DF_RGBA16_4444,
        /**< RGBA4444 16-bit - 4-bits R, 4-bits G, 4-bits B, 4-bit Alpha (LSB). */
        SYSTEM_DF_ARGB24_6666,
        /**< ARGB6666 24-bit - 6-bits R, 6-bits G, 6-bits B, 6-bit Alpha (MSB). */
        SYSTEM_DF_RGBA24_6666,
        /**< RGBA6666 24-bit - 6-bits R, 6-bits G, 6-bits B, 6-bit Alpha (LSB). */
        SYSTEM_DF_RGB24_888,
        /**< RGB24 24-bit - 8-bits R, 8-bits G, 8-bits B. */
        SYSTEM_DF_ARGB32_8888,
        /**< ARGB32 32-bit - 8-bits R, 8-bits G, 8-bits B, 8-bit Alpha (MSB). */
        SYSTEM_DF_RGBA32_8888,
        /**< RGBA32 32-bit - 8-bits R, 8-bits G, 8-bits B, 8-bit Alpha (LSB). */
        SYSTEM_DF_BGR16_565,
        /**< BGR565 16-bit -   5-bits B, 6-bits G, 5-bits R. */
        SYSTEM_DF_ABGR16_1555,
        /**< ABGR1555 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit Alpha (MSB). */
        SYSTEM_DF_ABGR16_4444,
        /**< ABGR4444 16-bit - 4-bits B, 4-bits G, 4-bits R, 4-bit Alpha (MSB). */
        SYSTEM_DF_BGRA16_5551,
        /**< BGRA5551 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit Alpha (LSB). */
        SYSTEM_DF_BGRA16_4444,
        /**< BGRA4444 16-bit - 4-bits B, 4-bits G, 4-bits R, 4-bit Alpha (LSB). */
        SYSTEM_DF_ABGR24_6666,
        /**< ABGR6666 24-bit - 6-bits B, 6-bits G, 6-bits R, 6-bit Alpha (MSB). */
        SYSTEM_DF_BGR24_888,
        /**< BGR888 24-bit - 8-bits B, 8-bits G, 8-bits R. */
        SYSTEM_DF_ABGR32_8888,
        /**< ABGR8888 32-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit Alpha (MSB). */
        SYSTEM_DF_BGRA24_6666,
        /**< BGRA6666 24-bit - 6-bits B, 6-bits G, 6-bits R, 6-bit Alpha (LSB). */
        SYSTEM_DF_BGRA32_8888,
        /**< BGRA8888 32-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit Alpha (LSB). */
        SYSTEM_DF_BITMAP8 = 0x2000,
        /**< BITMAP 8bpp. */
        SYSTEM_DF_BITMAP4_LOWER,
        /**< BITMAP 4bpp lower address in CLUT. */
        SYSTEM_DF_BITMAP4_UPPER,
        /**< BITMAP 4bpp upper address in CLUT. */
        SYSTEM_DF_BITMAP2_OFFSET0,
        /**< BITMAP 2bpp offset 0 in CLUT. */
        SYSTEM_DF_BITMAP2_OFFSET1,
        /**< BITMAP 2bpp offset 1 in CLUT. */
        SYSTEM_DF_BITMAP2_OFFSET2,
        /**< BITMAP 2bpp offset 2 in CLUT. */
        SYSTEM_DF_BITMAP2_OFFSET3,
        /**< BITMAP 2bpp offset 3 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET0,
        /**< BITMAP 1bpp offset 0 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET1,
        /**< BITMAP 1bpp offset 1 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET2,
        /**< BITMAP 1bpp offset 2 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET3,
        /**< BITMAP 1bpp offset 3 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET4,
        /**< BITMAP 1bpp offset 4 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET5,
        /**< BITMAP 1bpp offset 5 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET6,
        /**< BITMAP 1bpp offset 6 in CLUT. */
        SYSTEM_DF_BITMAP1_OFFSET7,
        /**< BITMAP 1bpp offset 7 in CLUT. */
        SYSTEM_DF_BITMAP8_BGRA32,
        /**< BITMAP 8bpp BGRA32. */
        SYSTEM_DF_BITMAP4_BGRA32_LOWER,
        /**< BITMAP 4bpp BGRA32 lower address in CLUT. */
        SYSTEM_DF_BITMAP4_BGRA32_UPPER,
        /**< BITMAP 4bpp BGRA32 upper address in CLUT. */
        SYSTEM_DF_BITMAP2_BGRA32_OFFSET0,
        /**< BITMAP 2bpp BGRA32 offset 0 in CLUT. */
        SYSTEM_DF_BITMAP2_BGRA32_OFFSET1,
        /**< BITMAP 2bpp BGRA32 offset 1 in CLUT. */
        SYSTEM_DF_BITMAP2_BGRA32_OFFSET2,
        /**< BITMAP 2bpp BGRA32 offset 2 in CLUT. */
        SYSTEM_DF_BITMAP2_BGRA32_OFFSET3,
        /**< BITMAP 2bpp BGRA32 offset 3 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET0,
        /**< BITMAP 1bpp BGRA32 offset 0 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET1,
        /**< BITMAP 1bpp BGRA32 offset 1 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET2,
        /**< BITMAP 1bpp BGRA32 offset 2 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET3,
        /**< BITMAP 1bpp BGRA32 offset 3 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET4,
        /**< BITMAP 1bpp BGRA32 offset 4 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET5,
        /**< BITMAP 1bpp BGRA32 offset 5 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET6,
        /**< BITMAP 1bpp BGRA32 offset 6 in CLUT. */
        SYSTEM_DF_BITMAP1_BGRA32_OFFSET7,
        /**< BITMAP 1bpp BGRA32 offset 7 in CLUT. */
        SYSTEM_DF_BAYER_RAW = 0x3000,
        /**< Bayer pattern. */
        SYSTEM_DF_RAW_VBI,
        /**< Raw VBI data. */
        SYSTEM_DF_RAW,
        /**< Raw data - Format not interpreted. */
        SYSTEM_DF_MISC,
        /**< For future purpose. */
        SYSTEM_DF_INVALID
        /**< Invalid data format. Could be used to initialize variables. */
    }System_VideoDataFormat;
    
    
    typedef enum
    {
        SYSTEM_STD_NTSC = 0u,
        /**< 720x480 30FPS interlaced NTSC standard. */
        SYSTEM_STD_PAL,
        /**< 720x576 30FPS interlaced PAL standard. */
    
        SYSTEM_STD_480I,
        /**< 720x480 30FPS interlaced SD standard. */
        SYSTEM_STD_576I,
        /**< 720x576 30FPS interlaced SD standard. */
    
        SYSTEM_STD_CIF,
        /**< Interlaced, 360x120 per field NTSC, 360x144 per field PAL. */
        SYSTEM_STD_HALF_D1,
        /**< Interlaced, 360x240 per field NTSC, 360x288 per field PAL. */
        SYSTEM_STD_D1,
        /**< Interlaced, 720x240 per field NTSC, 720x288 per field PAL. */
    
        SYSTEM_STD_480P,
        /**< 720x480 60FPS progressive ED standard. */
        SYSTEM_STD_480P_30,
        /**< 720x480 30FPS progressive ED standard. */
        SYSTEM_STD_576P,
        /**< 720x576 50FPS progressive ED standard. */
        SYSTEM_STD_576P_25,
        /**< 720x576 25FPS progressive ED standard. */
    
        SYSTEM_STD_720P_60,
        /**< 1280x720 60FPS progressive HD standard. */
        SYSTEM_STD_720P_50,
        /**< 1280x720 50FPS progressive HD standard. */
        SYSTEM_STD_720P_30,
        /**< 1280x720 30FPS progressive HD standard. */
        SYSTEM_STD_720P_25,
        /**< 1280x720 25FPS progressive HD standard. */
        SYSTEM_STD_720P_24,
        /**< 1280x720 24FPS progressive HD standard. */
    
        SYSTEM_STD_1080I_60,
        /**< 1920x1080 30FPS interlaced HD standard. */
        SYSTEM_STD_1080I_50,
        /**< 1920x1080 25FPS interlaced HD standard. */
    
        SYSTEM_STD_1080P_60,
        /**< 1920x1080 60FPS progressive HD standard. */
        SYSTEM_STD_1080P_50,
        /**< 1920x1080 50FPS progressive HD standard. */
    
        SYSTEM_STD_1080P_30,
        /**< 1920x1080 30FPS progressive HD standard. */
        SYSTEM_STD_1080P_25,
        /**< 1920x1080 25FPS progressive HD standard. */
        SYSTEM_STD_1080P_24,
        /**< 1920x1080 24FPS progressive HD standard. */
    
        /* Vesa standards from here Please add all SMTPE and CEA standard enums
           above this only. this is to ensure proxy Oses compatibility
         */
        SYSTEM_STD_VGA_60 = 0x100,
        /**< 640x480 60FPS VESA standard. */
        SYSTEM_STD_VGA_72,
        /**< 640x480 72FPS VESA standard. */
        SYSTEM_STD_VGA_75,
        /**< 640x480 75FPS VESA standard. */
        SYSTEM_STD_VGA_85,
        /**< 640x480 85FPS VESA standard. */
    
        SYSTEM_STD_WVGA_60,
        /**< 800x480 60PFS WVGA */
    
        SYSTEM_STD_SVGA_60,
        /**< 800x600 60FPS VESA standard. */
        SYSTEM_STD_SVGA_72,
        /**< 800x600 72FPS VESA standard. */
        SYSTEM_STD_SVGA_75,
        /**< 800x600 75FPS VESA standard. */
        SYSTEM_STD_SVGA_85,
        /**< 800x600 85FPS VESA standard. */
    
        SYSTEM_STD_WSVGA_70,
        /**< 1024x600 70FPS standard. */
    
        SYSTEM_STD_XGA_60,
        /**< 1024x768 60FPS VESA standard. */
        SYSTEM_STD_XGA_70,
        /**< 1024x768 72FPS VESA standard. */
        SYSTEM_STD_XGA_75,
        /**< 1024x768 75FPS VESA standard. */
        SYSTEM_STD_XGA_85,
        /**< 1024x768 85FPS VESA standard. */
    
        SYSTEM_STD_1368_768_60,
        /**< 1368x768 60 PFS VESA>*/
        SYSTEM_STD_1366_768_60,
        /**< 1366x768 60 PFS VESA>*/
        SYSTEM_STD_1360_768_60,
        /**< 1360x768 60 PFS VESA>*/
    
        SYSTEM_STD_WXGA_60,
        /**< 1280x768 60FPS VESA standard. */
        SYSTEM_STD_WXGA_75,
        /**< 1280x768 75FPS VESA standard. */
        SYSTEM_STD_WXGA_85,
        /**< 1280x768 85FPS VESA standard. */
    
        SYSTEM_STD_1440_900_60,
        /**< 1440x900 60 PFS VESA>*/
    
        SYSTEM_STD_SXGA_60,
        /**< 1280x1024 60FPS VESA standard. */
        SYSTEM_STD_SXGA_75,
        /**< 1280x1024 75FPS VESA standard. */
        SYSTEM_STD_SXGA_85,
        /**< 1280x1024 85FPS VESA standard. */
    
        SYSTEM_STD_WSXGAP_60,
        /**< 1680x1050 60 PFS VESA>*/
    
        SYSTEM_STD_SXGAP_60,
        /**< 1400x1050 60FPS VESA standard. */
        SYSTEM_STD_SXGAP_75,
        /**< 1400x1050 75FPS VESA standard. */
    
        SYSTEM_STD_UXGA_60,
        /**< 1600x1200 60FPS VESA standard. */
        
        SYSTEM_STD_WUXGA_60,
        /**< 1920x1200 60FPS VESA standard. */
    
        /* Multi channel standards from here Please add all VESA standards enums
           above this only. this is to ensure proxy Oses compatibility */
        SYSTEM_STD_MUX_2CH_D1 = 0x200,
        /**< Interlaced, 2Ch D1, NTSC or PAL. */
        SYSTEM_STD_MUX_2CH_HALF_D1,
        /**< Interlaced, 2ch half D1, NTSC or PAL. */
        SYSTEM_STD_MUX_2CH_CIF,
        /**< Interlaced, 2ch CIF, NTSC or PAL. */
        SYSTEM_STD_MUX_4CH_D1,
        /**< Interlaced, 4Ch D1, NTSC or PAL. */
        SYSTEM_STD_MUX_4CH_CIF,
        /**< Interlaced, 4Ch CIF, NTSC or PAL. */
        SYSTEM_STD_MUX_4CH_HALF_D1,
        /**< Interlaced, 4Ch Half-D1, NTSC or PAL. */
        SYSTEM_STD_MUX_8CH_CIF,
        /**< Interlaced, 8Ch CIF, NTSC or PAL. */
        SYSTEM_STD_MUX_8CH_HALF_D1,
        /**< Interlaced, 8Ch Half-D1, NTSC or PAL. */
        SYSTEM_STD_MUX_4CH_960H,
        /**< Interlaced ,4Ch 960H , NTSC or PAL */
    
        /* Auto detect and Custom standards Please add all multi channel standard
           enums above this only. this is to ensure proxy Oses compatibility */
        SYSTEM_STD_AUTO_DETECT = 0x300,
        /**< Auto-detect standard. Used in capture mode. */
        SYSTEM_STD_CUSTOM,
        /**< Custom standard used when connecting to external LCD etc...
             The video timing is provided by the application.
             Used in display mode. */
        SYSTEM_STD_INVALID = 0xFFFF
        /**< Invalid standard used for initializations and error checks*/
    
    } SYSTEM_Standard;
    
    
    typedef unsigned char uint8_t;
    typedef unsigned short uint16_t;
    typedef unsigned int uint32_t;
    
    typedef struct  SII9233_video_status{
        uint32_t isVideoDetect;
        uint32_t frameWidth;
        uint32_t frameHeight;
        uint32_t frameInterval;
        uint32_t isInterlaced;
    }SII9233_video_status_t;
    
    typedef struct  SII9233_chip_info{
        uint32_t chipId;
        uint32_t chipRevision;
        uint32_t firmwareVersion;
    }SII9233_chip_info_t;
    
    typedef struct SII9233_av_info{
        uint32_t colorSpace;          /* RGB444 ot YUV422 or YUV422 */
        uint32_t colorImetric;        /* BT709 or BT601 */
        uint32_t pixelRepeat;         /* 1x, 2x, 4x */
        uint32_t detected;            /* detected or hard code*/
    } SII9233_av_info_t;
    
    typedef struct SII9233_Dev {
        int i2c_dev_fd;
        char i2c_dev_name[32];
        uint8_t first_dev_addr;     //0x62
        uint8_t second_dev_addr;    //0x6a
    
        uint8_t xv_color_addr;  //0x64
        uint8_t edid_addr;      //0xe0
        uint8_t cec_addr;       //0xc0
        uint8_t regaddr[0x100];
        uint8_t regdata[0x100];
    
        SII9233_chip_info_t chip_info;
        SII9233_video_status_t video_status;
        SII9233_av_info_t av_info;
        bool isPalMode;
        System_VideoDataFormat videoDataFormat;
        SYSTEM_Standard standard;
    }SII9233_Dev_t;
    
    int sii9233_api_init(SII9233_Dev_t *pdev);
    int sii9233_api_deinit(SII9233_Dev_t *pdev);
    int sii9233_api_start(SII9233_Dev_t *pdev);
    int sii9233_api_stop(SII9233_Dev_t *pdev);
    
    #endif
    
    展开全文
  • Hi3531DV100 H.265编解码处理器简介 Hi3531DV100 H.265编解码处理器简介 Hi3531DV100 H.265编解码处理器简介
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  • 硬件环境:HI3559A+HI3531D通过PCIE级联 问题1 从片HI3531D 通过PCIE 加载程序后开机纸打印 startup 无法进入u-boot 解决方法: 1.查看复位信号正常 2.查看供电正常 3.查看晶振正常 4.从片HI3531D修改启动...

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