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  • rk瑞芯微的基于Android的mipi初始化序列化转为dts格式的文档,该文档经过rk Android8.1调试测试过。
  • 批量初始化序列初始值 无 DECLARE TYPE tsi IS RECORD( t VARCHAR2(100) , s VARCHAR2(100), i varchar2(100)); tsiTemp tsi; maxId varchar2(20);BEGIN for tsiTemp in ( select 'T_xxxx_CONFIG'as t,'SEQ_xxxxx_ID...

    批量初始化序列初始值 无 DECLARE TYPE tsi IS RECORD( t VARCHAR2(100) , s VARCHAR2(100), i varchar2(100)); tsiTemp tsi; maxId varchar2(20);BEGIN for tsiTemp in ( select 'T_xxxx_CONFIG'as t,'SEQ_xxxxx_ID' as s,'xxxx_ID' as i from dual union se

    批量初始化序列初始值

    DECLARE

    TYPE tsi IS RECORD(

    t VARCHAR2(100) ,

    s VARCHAR2(100),

    i varchar2(100));

    tsiTemp tsi;

    maxId varchar2(20);

    BEGIN

    for tsiTemp in (

    select 'T_xxxx_CONFIG'as t,'SEQ_xxxxx_ID' as s,'xxxx_ID' as i from dual

    union

    select 'T_ttttt_INFO'as t,'SEQ_ttttt_ID' as s,'tttt_ID' as i from dual

    union

    select 'T_ddddd_LOG' as t,'SEQ_dddddd_ID' as s,'dddd_ID' as i from dual

    )

    loop

    execute immediate 'select nvl(max('||tsiTemp.i||'+1),1) from '||tsiTemp.t into maxId;

    execute immediate 'drop sequence '||tsiTemp.s;

    execute immediate 'create sequence '||tsiTemp.s

    || ' minvalue '||maxId

    || ' maxvalue 999999999999999999999999999 '

    || ' start with '||maxId

    || ' increment by 1'

    ||' cache 20'

    ||' order';

    end loop;

    END;

    f68f2add0b68e4f9810432fce46917b7.png

    本文原创发布php中文网,转载请注明出处,感谢您的尊重!

    展开全文
  • RK平台mipi屏初始化序列都是在dts中进行配置,有两种方式,下面分别介绍两种方式的配置方法。 方式一 RK平台较老的SDK采用下面方式配置mipi参数,如:RK3128 5.1 SDK中就是采用的下面方式。 示例: / { /* ...

    RK平台mipi屏初始化序列都是在dts中进行配置,有两种方式,下面分别介绍两种方式的配置方法。

    方式一

    RK平台较老的SDK采用下面方式配置mipi参数,如:RK3128 5.1 SDK中就是采用的下面方式。

    示例:

    / {
        /* about mipi */
        disp_mipi_init: mipi_dsi_init{
            compatible = "rockchip,mipi_dsi_init";
            rockchip,screen_init    = <1>;
            rockchip,dsi_lane       = <4>;
            rockchip,dsi_hs_clk     = <550>;
            rockchip,mipi_dsi_num   = <1>;
        };
        
        disp_mipi_power_ctr: mipi_power_ctr {
            compatible = "rockchip,mipi_power_ctr";
            
            /*
            mipi_lcd_rst:mipi_lcd_rst{
                compatible = "rockchip,lcd_rst";
                rockchip,gpios = <&gpio2 GPIO_D1 GPIO_ACTIVE_HIGH>;
                rockchip,delay = <20>;
            };
            
            mipi_lcd_en:mipi_lcd_en {
                compatible = "rockchip,lcd_en";
                rockchip,gpios = <&gpio2 GPIO_D0 GPIO_ACTIVE_LOW>;
                rockchip,delay = <100>;
            };
            */
        };
        
        disp_mipi_init_cmds: screen-on-cmds {
            compatible = "rockchip,screen-on-cmds";
            rockchip,cmd_debug = <1>;
            
            rockchip,on-cmds1 {
                compatible = "rockchip,on-cmds";
                rockchip,cmd_type = <LPDT>;
                rockchip,dsi_id = <0>;
                rockchip,cmd = <0x15 0xE0 0x00>;
                rockchip,cmd_delay = <0>;
            };
            
            rockchip,on-cmds2 {
                compatible = "rockchip,on-cmds";
                rockchip,cmd_type = <LPDT>;
                rockchip,dsi_id = <0>;
                rockchip,cmd = <0x39 0x55 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10>;
                rockchip,cmd_delay = <0>;
            };
    
            //SLP OUT
            rockchip,on-cmds3 {
                compatible = "rockchip,on-cmds";
                rockchip,cmd_type = <LPDT>;
                rockchip,dsi_id = <0>;
                rockchip,cmd = <0x05 0x11>;
                rockchip,cmd_delay = <120>;
            };
    
            //DISP ON
            rockchip,on-cmds4 {
                compatible = "rockchip,on-cmds";
                rockchip,cmd_type = <LPDT>;
                rockchip,dsi_id = <0>;
                rockchip,cmd = <0x05 0x29>;
                rockchip,cmd_delay = <5>;
            };
        };
    
        disp_timings: display-timings {
            native-mode = <&timing0>;
            compatible = "rockchip,display-timings";
            timing0: timing0 {
                screen-type = <SCREEN_MIPI>;
                lvds-format = <LVDS_8BIT_2>;
                out-face    = <OUT_P888>;
                
                clock-frequency = <67330000>;
                hactive = <800>;             
                vactive = <1280>;       
                hback-porch = <18>;           
                hfront-porch = <18>;          
                vback-porch = <10>;         
                vfront-porch = <20>;          
                hsync-len = <18>;            
                vsync-len = <4>;
                
                hsync-active = <0>;
                vsync-active = <0>;
                de-active = <0>;
                pixelclk-active = <0>;
                swap-rb = <0>;
                swap-rg = <0>;
                swap-gb = <0>;
            };
        };
    };

    这里只分析disp_mipi_init_cmds的配置规则,disp_mipi_init、disp_mipi_power_ctl、disp_timings不分析,其中disp_timings可以参考“如何确定lcd timing参数”。

    下面代码段为一条mipi初始化数据,主要关心的参数有“rockchip,cmd”和“rockchip,cmd_delay”。

    rockchip,on-cmds1 {
        compatible = "rockchip,on-cmds";
        rockchip,cmd_type = <LPDT>;
        rockchip,dsi_id = <0>;
        rockchip,cmd = <0x15 0xE0 0x00>;
        rockchip,cmd_delay = <0>;
    };

    rockchip,cmd

    命令格式如下:

    0x15 0xE0 0x00
     |     |   |
     |     |   数据
     |     寄存器地址
     命令类型(0x05: 单字节数据 0x15: 双字节数据 0x39: 多字节数据)

    单字节数据举例:

    rockchip,on-cmds3 {
        compatible = "rockchip,on-cmds";
        rockchip,cmd_type = <LPDT>;
        rockchip,dsi_id = <0>;
        rockchip,cmd = <0x05 0x11>;
        rockchip,cmd_delay = <120>;
    };

    双字节数据举例:

    rockchip,on-cmds1 {
        compatible = "rockchip,on-cmds";
        rockchip,cmd_type = <LPDT>;
        rockchip,dsi_id = <0>;
        rockchip,cmd = <0x15 0xE0 0x00>;
        rockchip,cmd_delay = <0>;
    };

    多字节数据举例:

    rockchip,on-cmds2 {
        compatible = "rockchip,on-cmds";
        rockchip,cmd_type = <LPDT>;
        rockchip,dsi_id = <0>;
        rockchip,cmd = <0x39 0x55 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10>;
        rockchip,cmd_delay = <0>;
    };

    rockchip,cmd_delay

    此字段定义发送完命令后延时时长,单位毫秒(ms),大部分命令无须延时。

    方式二

    RK平台新的SDK已经统一采用下面方式配置mipi参数,如:RK3288 8.1 SDK中就是采用的下面方式。

    示例:

    &dsi0 {
        status = "okay";
        rockchip,lane-rate = <600>;
    
        panel: panel {
            compatible = "simple-panel-dsi";
            reg = <0>;
            backlight = <&backlight>;
            enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
            //reset-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
            power-supply = <&vcc_lcd>;
            dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>;
            dsi,format = <MIPI_DSI_FMT_RGB888>;
            dsi,lanes = <4>;
            reset-delay-ms = <20>;
            init-delay-ms = <20>;
            enable-delay-ms = <120>;
            prepare-delay-ms = <120>;
            status = "okay";
        
            panel-init-sequence = [
                15 00 02 80 77
                15 00 02 81 77
                15 00 02 82 77
                15 00 02 83 77
                15 00 02 84 77
                15 00 02 85 77
                15 00 02 86 77
                05 64 01 11
                05 14 01 29
            ];
    
            panel-exit-sequence = [
                05 64 01 28
                05 96 01 10
            ];
    
            disp_timings: display-timings {
                native-mode = <&timing2>;
                timing2: timing0 {
                    clock-frequency = <52000000>;
                    hactive = <1024>;
                    vactive = <600>;
                    hback-porch = <160>;
                    hfront-porch = <160>;
                    vback-porch = <23>;
                    vfront-porch = <12>;
                    hsync-len = <10>;
                    vsync-len = <10>;
                    hsync-active = <0>;
                    vsync-active = <0>;
                    de-active = <0>;
                    pixelclk-active = <0>;
                };
            };
        };
    };

    这里依然只分析panel-init-sequence和panel-exit-sequence的配置规则,其它配置可以参考“如何确定lcd timing参数”。

    新的mipi初始化序列配置规则与老方法其实是一致的,只是改写了表达方式,如下:

    panel-init-sequence = [
        15 00 02 80 77
        15 00 02 81 77
        15 00 02 82 77
        15 00 02 83 77
        15 00 02 84 77
        15 00 02 85 77
        15 00 02 86 77
        39 00 0D C3 01 66 13 23 00 66 85 33 20 38 38 00
        05 64 01 11
        05 14 01 29
    ];

    中括号里的内容,每一行表示一串命令字,规则如下:

    15 00 02 80 77
     |  |  | |  |
     |  |  | |  数据
     |  |  | | 寄存器地址
     |  |  数据长度
     |  延时
     命令类型(0x05: 单字节数据 0x15: 双字节数据 0x39: 多字节数据)

    单字节数据举例:

    05 64 01 11

    双字节数据举例:

    15 00 02 86 77

    多字节数据举例:

    39 00 0D C3 01 66 13 23 00 66 85 33 20 38 38 00

     

    如何确定lcd timing参数

    这里以Rockchip平台为例,Rockchip平台lcd timing常见参数配置如下:

    disp_timings: display-timings {
        native-mode = <&timing0>;
        timing0: timing0 {
            clock-frequency = <31000000>;
            hactive = <480>;
            vactive = <854>;
            hback-porch = <24>;
            hfront-porch = <72>;
            vback-porch = <10>;
            vfront-porch = <12>;
            hsync-len = <24>;
            vsync-len = <2>;
            hsync-active = <0>;
            vsync-active = <0>;
            de-active = <0>;
            pixelclk-active = <0>;
        };
    };

    常规参数

    其中以下参数根据屏的规格书填写:

    hactive = <480>;        // 分辨率-宽
    vactive = <854>;        // 分辨率-高
    hback-porch = <24>;     // 行可视范围前肩
    hfront-porch = <72>;    // 行可视范围后肩
    vback-porch = <10>;     // 帧可视前肩
    vfront-porch = <12>;    // 帧可视后肩
    hsync-len = <24>;       // 行同步肪冲宽度
    vsync-len = <2>;        // 场同步脉冲宽度

    以下参数表示对应信号的有效电平,默认为低电平(0):

    hsync-active = <0>;     // 行同步信号
    vsync-active = <0>;     // 场同步信号
    de-active = <0>;        // de信号
    pixelclk-active = <0>;  // clk信号

    clock-frequency 的计算方法

    已知下面参数:

    • fps: 屏幕刷新率(默认:60帧)
    • htotal: hactive + hback-porch + hfront-porch + hsync-len
    • vtotal: vactive + hfront-porch + vfront-porch + vsync-len

    求clock-frequency公式如下:

    htotal * vtotal * fps = clock-frequency

    按照上面参考参数计算如下:

    (480 + 24 + 72 + 24) x (854 + 10 + 12 + 2) x 60 = 31608000

    计算出来的准确值为31608000,我们取整:

    clock-frequency = <31000000>;

    dsi_hs_clk 的计算方法

    100 + ((htotal * vtotal * fps) * 3 * 8 / lanes)

     

    展开全文
  • 在函数中board_init_f()中,进行了一系列的初始化,主要通过调用初始化序列中的函数来实现。 初始化序列定义如下,这里只留下了我用到的初始化函数: init_fnc_t *init_sequence[] = { get_clocks,

    http://www.360doc.com/content/12/0825/03/7775902_232197662.shtml


    在函数中board_init_f()中,进行了一系列的初始化,主要通过调用初始化序列中的函数来实现。

    初始化序列定义如下,这里只留下了我用到的初始化函数:

    init_fnc_t *init_sequence[] = {
    get_clocks,  
    init_timebase,
    env_init,
    init_baudrate,
    serial_init,
    console_init_f,
    display_options,
    checkcpu,
    checkboard,
    init_func_i2c,
    init_func_ram,
    NULL,   /* Terminate this list */
    };

    下面逐个对这些函数进行说明:

    get_clocks在文件./include/common.h中定义,在文件./cpu/mpc824x/Speed.c中实现,用于设置global_data中的gd->cpu_clk和gd->bus_clk。

    init_timebase在文件./include/common.h中定义,在文件./lib_ppc/time.c中实现,用于设置Time Base寄存器TBU和TBL,将其都设置成0。

    env_init在文件./include/common.h中定义,在文件./common/Env_flash.c中实现,用于设置global_data中的gd->env_addr和gd->env_valid。

    init_baudrate在文件./lib_ppc/board.c中定义和实现,用于设置global_data中的gd->baudrate。

    serial_init在文件./include/common.h中定义,在文件./drivers/serial.c中实现,通过调用函数 NS16550_init,对UART相关的寄存器进行初始化。NS16550_init在文件./include/ns16550.h中定义,在文件. /drivers/ns16550.c中实现。

    console_init_f在文件./include/common.h中定义,在文件./common/console.c中实现,用于设置global_data中的gd->have_console。

    display_options在文件./include/common.h中定义,在文件./lib_generic/display_options.c中实现,用于打印版本信息version_string。

    checkcpu在文件./include/common.h中定义,在文件./cpu/mpc824x/cpu.c中实现,用于检测并打印CPU版本、CPU时钟频率、Cache大小等信息。

    checkboard在文件./include/common.h中定义,在文件. /board/sandpoint/sandpoint.c中实现,用于打印板子名称等信息。

    init_func_i2c在文件./include/common.h中定义和实现。其中调用i2c_ini,用于初始化I2C单元相关的寄存器。 i2c_init在文件./include/i2c.h中定义,在文件./cpu/mpc824x/drivers/i2c/i2c.c中实现。

    init_func_ram在文件./lib_ppc/board.c中定义和实现。其中调用initdram,initdram在文件. /include/common.h中定义,在文件. /board/sandpoint/sandpoint.c中实现。Initdram又调用get_ram_size,get_ram_size在在文 件./include/common.h中定义,在文件. /common/memsize.c中实现,用于检测实际可用RAM的大小。【get_ram_size函数首先将特定的数据分别写入地址 0,1,2,4,8,……处,然后依次读出。如果读出的数据和之前写入的数据一致,则可用内存大小倍增,如果不一致,则说明该内存位置不可用,以后的就不 再检测了。这样可用的内存大小就是(0,1,2,4,8,……)×sizeof(long)中的某一个值。之后,init_func_ram打印可用 RAM大小】【此为UBOOT检测内存大小的原理】。

    展开全文
  • MIPI DSI 和 D-PHY 初始化序列 2015-12-29 深圳 南山平山村 曾剑锋 参考文档: i.MX 6Dual/6Quad Multimedia Applications Processor ...
                                       MIPI DSI 和 D-PHY 初始化序列
    
    
                                                  2015-12-29 深圳 南山平山村 曾剑锋
    
    参考文档:
        i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual
    
    43.4 Programming
        43.4.1 DSI and D-PHY initialization sequence
        43.4.1 DSI 和 D-PHY 初始化序列
        This chapter describes the procedure for DSI and D-PHY initialization. This process is based on APB register interface access.
        这一章描述了DSI和D-PHY初始化的过程。处理过程是基于APB注册接口访问。
            • By default register PHY_RSTZ is activating the PHY resets physhutdownz, phyrstz and disabling enableclk and register PHY_TEST_CTRL0 is by default asserting the testclr pin. All the PHY reset pins are being activated by default.
            默认情况下PHY_RSTZ寄存器已经重置PHY physhutdownz,phyrstz和禁用enableclk,寄存器PHY_TEST_CTRL0是默认情况下关闭testclr引脚的。所有的phy resset引脚默认都是激活的。
                +---------------------------------------------------------------+
                |             MIPI_DSI_PHY_RSTZ field descriptions              |
                +---------------+-----------------------------------------------+
                | Field         | Description                                   | 
                +---------------+-----------------------------------------------+
                | 313          |                                               | 
                |   -           | Reserved                                      | 
                +---------------+-----------------------------------------------+
                |   2           |                                               | 
                | phy_enableclk | Enables D-PHY Clock Lane Module when 1        | 
                +---------------+-----------------------------------------------+
                |   1           | D-PHY Reset disable when 1, used to place the | 
                | phy_rstz      | digital section of D-PHY in reset state       | 
                +---------------+-----------------------------------------------+
                |   0           | D-PHY Shutdown disable when 1, used to place  | 
                | phy_shutdownz | the complete D-PHY macro in power down        | 
                +---------------+-----------------------------------------------+
    
            • Configure Register PHY_IF_CFG with correct the number of lanes to be used by the controller.
            通过配置PHY_IF_CFG寄存器来配置控制器的lane的数量。
                +-------------------------------------------------------------------+
                |           MIPI_DSI_PHY_IF_CFG_ field descriptions                 |
                +----------------+--------------------------------------------------+
                |   Field        |                    Description                   |
                +----------------+--------------------------------------------------+
                |    3110       |                                                  | 
                |      -         | Reserved                                         | 
                +----------------+--------------------------------------------------+
                |     92        | Configures minimum wait period to request an HS  | 
                | phy_stop_wait_ | transmission after the stop state accounted in   | 
                |      time      | clock lane cycles                                | 
                +----------------+--------------------------------------------------+
                |     10        | Number of active data lanes.                     | 
                |    n_lanes     | 00 1 Data Lane (Lane 0)                          | 
                |                | 01 2 Data Lanes (Lane 0, and 1)                  | 
                |                | 10 3 Data Lanes (Lane 0,1 and 2)                 | 
                |                | 11 4 Data Lanes (All)                            | 
                +----------------+--------------------------------------------------+
    
            • Configure the TX_ESC clock frequency to a frequency lower than 20MHz that is the maximum allowed frequency for D-PHY ESCAPE mode. This is done by writing in Register CLKMGR_CFG, field TX_ESC_CLK_DIVISION.  TX_ESC_CLK_DIVISION divides Byte Clock and generates a TX_ESC clock for the D-PHY. (Note: Byte clock is limited to 125MHz (1GHz/8bits) and by writing TX_ESC_CLK_DIVISION=0x07 TX_ESC clock will always be lower than 20MHz)
            配置TX_ESC时钟频率小于20MHz给D-PHY ESCAPE模式,通过向CLKMGR_CFG寄存器的TX_ESC_CLK_DIVISION进行配置。TX_ESC_CLK_DIVISION对Byte Clock进行分频,并对生成TX_ESC时钟给D-PHY。(注意:Byte clock被限制在125MHz(1GHz/8bit),并且对TX_ESC_CLK_DIVISION=0x07 TX_ESC 时钟将总是小于20MHz)
                +-------------------------------------------------------------------+
                |            MIPI_DSI_CLKMGR_CFG field descriptions                 |
                +-------------+-----------------------------------------------------+
                |   Field     |   Description                                       | 
                +-------------+-----------------------------------------------------+
                |   3116     |                                                     | 
                |     -       | Reserved                                            | 
                +-------------+-----------------------------------------------------+
                |   158      | Division factor for Time Out clock used as timing   | 
                | TO_CLK_     | unit in the configuration of HS to LP and LP to HS  | 
                | DIVIDSION   | transition error.                                   | 
                +-------------+-----------------------------------------------------+
                |     70     | Division factor for TX ESCAPE clock source (        | 
                | TX_ESC_CLK_ | lanebyteclk pin), values 0 and 1 stop TX_ESC        | 
                | DIVIDSION   | clock generation.                                   | 
                +-------------+-----------------------------------------------------+
    
            • Configure the DPHY PLL clock frequency through the TEST Interface to operate at 1GHz, assuming that the REF_CLK is provided with a frequency of 27MHz
            假设REF_CLk提供的27MHz频率,通过TEST接口操作配置DPHY PLL时钟频率达到1GHz。
                +---------------------------------------------------------------------------+
                |         MIPI_DSI_PHY_TST_CTRL0 field descriptions                         |
                +-------------+-------------------------------------------------------------+
                |   Field     | Description                                                 | 
                +-------------+-------------------------------------------------------------+
                |    312     |                                                             | 
                |      -      | Reserved                                                    | 
                +-------------+-------------------------------------------------------------+
                |      1      | PHY test interface strobe signal. Used to clock TESTDIN bus | 
                | phy_testclk | into the D-PHY. In conjunction with TESTEN signal controls  | 
                |             | the operation selection                                     | 
                +-------------+-------------------------------------------------------------+
                |      0      | PHY test interface clear. When active performs vendor       | 
                | phy_testclr | specific interface initialization (Active High)             | 
                +-------------+-------------------------------------------------------------+
    
                +----------------------------------------------------------------------------------+
                |                MIPI_DSI_PHY_TST_CTRL1 field descriptions                         |
                +--------------+-------------------------------------------------------------------+
                |    Field     | Description                                                       | 
                +--------------+-------------------------------------------------------------------+
                |    3117     |                                                                   | 
                |     -        | Reserved                                                          | 
                +--------------+-------------------------------------------------------------------+
                |     16       | PHY test interface operation selector: when 1 configures address  | 
                | phy_testen   | write operation on the falling edge of TESTCLK; when 0 configures | 
                |              | a data write operation on the rising edge of TESTCLK              | 
                +--------------+-------------------------------------------------------------------+
                |    158      | PHY output 8-bit data bus for read-back and internal probing      | 
                | phy_testdout | functionalities                                                   | 
                +--------------+-------------------------------------------------------------------+
                |     70      | PHY test interface input 8-bit data bus for internal register     | 
                | phy_testdin  | programming and test functionalities access                       | 
                +--------------+-------------------------------------------------------------------+
    
                • Write @ PHY_TST_CTRL0 - 32'h00000000 this disables the testclr pin enabling the interface to write new values to the DPHY internal registers.
                往PHY_TST_CTRL0写入32'h00000000,禁用testclr引脚,同时使能接口往DPHY内部寄存器中写值
                • Write @ PHY_TST_CTRL1 - 32'h00010044 this enables the testen pin bit 17 of this Core register and configures the testdatain to 8'h44. This operation initiate the configuration process of the test code number 0x44.
                往PHY_TST_CTRL1写入32'h00010044,使能testen引脚核心寄存器17位,并配置testdatain值为8'h44,这个操作启动配置test code number 0x44。
                • Write @ PHY_TEST_CTRL0 - 32'h0000002 followed by a new write to PHY_TEST_CTRL0 - 32'h00000000. This operation toggles the testclk (bit 2) and the testdin will be sampled on the falling edge of testclk latching a new test code.
                往PHY_TST_CTRL0写入32'h00000002总是跟随在往PHY_TST_CTRL0写入32'h00000000之后,这个操作触发testclk(bit2),并将testddatain的数据采样生成一个新的test code
                • Write @ PHY_TEST_CTRL1 - 32'h00000074 disabling the testen pin and configuring testdatain to 8'h74. This operation prepares the interface to load in test code 0x44 the 0x74 value.
                • Write @ PHY_TEST_CTRL0 - 32'h00000002 followed by a new write to PHY_TEST_CTRL0 - 32'h00000000. This operation toggles the testclk and the testdin will be sampled on the rising edge of testclk latching a new content data to the configured test code.
            • Write @ PHY_RSTZ - 32'h00000007. This operation asserts physhutdownz, phyrstz and enableclk releasing the PHY from power down. The PHY will startup the PLL locking procedure to 1GHz operation.
            往PHY_RSTZ写入32'h00000007这操作打断physhutdownz, phyrstz和使能时钟,让PHY从断电状态恢复,PHY将重启PLL锁到1GHz操作。
            • Read @ PHY_STATUS - 32'hxxxxxxx1, until bit 0 phylock is detected at 1 signaling that PLL is locked and that a stable byte clock is being provided to the DSI host controller.
            读取PHY_STATUS的值32'hxxxxxxx1,直到该寄存器的bit 0位被检查到1,说明PLL的锁住了,并且其在一个稳定的byte clock可以被提供到DSI主控制器
            • Read @ PHY_STATUS - 32'hxxxxx1x1, until bit 2 phystopstateclklane is read '1' identifying that Clock Lane is in Stop State. Clock lane need to be in Stop state so that the D-PHY can switch to other operational states such as the High Speed mode.
            读取PHY_STATUS的值32'hxxxxx1x1,直到该寄存器的bit 2位被检查到1,确定Clock lane在Stop状态。Clock lane需要进入Stop状态,这样D-PHY才能切换到其他的操作状态,如:High Speed mode。
            • Write register PHY_IF_CTRL bit 0 to generate High Speed clock (txrequestHSclk).
            往PHY_IF_CTRL中bit 0写入1,生成High Speed clock(txrequestHSclk)。
            • Only after: 1) PLL locked and 2) Clock lane in Stop-State; the PHY will drive the correct LP sequence to configure the receiver end for HS.
            只有在以下条件下继续运行:
                1. PLL被锁住;
                2. Clock lane进入Stop-State状态,PHY将驱动正确的LP序列去配置从设备,并进入HS状态。
            • D-PHY starts transmitting HS clock on the Clock Lane.
            D-PHY 开始传送HS clock在Clock Lane上面。

     

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