精华内容
下载资源
问答
  • Verilog 实现 VGA 接口时序

    千次阅读 2019-12-10 22:23:02
    在上一篇中了解了 VGA 的时序(VGA 时序分析),这里可以使用 Verilog 写一个 VGA 的时序,那么需要控制: HSYNC VSYNC RGB 信号首先查看原理图: 对应到芯片管脚的: HSYNC---P123 VSYNC---P124 VGA_R-...

    在上一篇中了解了 VGA 的时序(VGA 时序分析),这里可以使用 Verilog 写一个 VGA 的时序,那么需要控制:

    HSYNC

    VSYNC

    RGB

    信号首先查看原理图:

    对应到芯片管脚的:

    HSYNC---P123

    VSYNC---P124

    VGA_R---P26

    VGA_G---P22

    VGA_B---P23

    所以管脚约束 ucf 文件为:

    ##########################################################
    #Clock&Rst
    NET "ext_clk_25m" LOC = P23;
    NET "ext_clk_25m" IOSTANDARD = LVCMOS33;
    NET "ext_rst_n" LOC = P24;
    NET "ext_rst_n" IOSTANDARD = LVCMOS33;
    
    ##########################################################
    #VGA interface
    NET "vga_r"			LOC=P26   | IOSTANDARD = LVCMOS33;
    NET "vga_g"			LOC=P22   | IOSTANDARD = LVCMOS33;
    NET "vga_b"			LOC=P21   | IOSTANDARD = LVCMOS33;
    NET "vga_hsy"		LOC=P123   | IOSTANDARD = LVCMOS33;
    NET "vga_vsy"		LOC=P124   | IOSTANDARD = LVCMOS33;
    

    由于不同的 VGA 分辨率对应的本地时钟不一样,为了支持多个分辨率,那么需要配置 PLL 输出为多个不同的时钟,顶层文件负责连接 PLL 和 VGA 模块:

    时钟信号通过 PLL 直接给到 vga 模块,同时 LOCKED 信号作为 VGA 模块的复位信号:

    顶层文件的实现如上述所示:

    module sp6(
    			input ext_clk_25m,	//外部输入25MHz时钟信号
    			input ext_rst_n,	//外部输入复位信号,低电平有效
    			output vga_r,	//VGA显示色彩R
    			output vga_g,	//VGA显示色彩G
    			output vga_b,	//VGA显示色彩B
    			output vga_hsy,	//VGA显示行同步信号
    			output vga_vsy	//VGA显示场同步信号
    		);													
    
    //-------------------------------------
    //PLL例化
    wire clk_25m;	//PLL输出25MHz时钟
    wire clk_50m;	//PLL输出50MHz时钟
    wire clk_65m;	//PLL输出65MHz时钟
    wire clk_108m;	//PLL输出108MHz时钟
    wire clk_130m;	//PLL输出130MHz时钟
    wire sys_rst_n;	//PLL输出的locked信号,作为FPGA内部的复位信号,低电平复位,高电平正常工作
    
      pll_controller uut_pll_controller
       (// Clock in ports
        .CLK_IN1(ext_clk_25m),      // IN
        // Clock out ports
        .CLK_OUT1(clk_12m5),     // OUT
        .CLK_OUT2(clk_25m),     // OUT
        .CLK_OUT3(clk_50m),     // OUT
        .CLK_OUT4(clk_65m),     // OUT
    	.CLK_OUT5(clk_108m),     // OUT
    	.CLK_OUT6(clk_130m),     // OUT
        // Status and control signals
        .RESET(~ext_rst_n),// IN
        .LOCKED(sys_rst_n));      // OUT		
    		
    
    //-------------------------------------
    //VGA驱动时序产生,显示Color bar
    
    vga_controller	uut_vga_controller(
    				.clk_25m(clk_25m),
    				.clk_50m(clk_50m),
    				.clk_65m(clk_65m),
    				.clk_108m(clk_108m),
    				.clk_130m(clk_130m),
    				.rst_n(sys_rst_n),
    				.vga_r(vga_r),
    				.vga_g(vga_g),
    				.vga_b(vga_b),
    				.vga_hsy(vga_hsy),
    				.vga_vsy(vga_vsy)
    			);

    vga_controller 的实现为:

    module vga_controller(
    			input clk_25m,	//PLL输出25MHz时钟
    			input clk_50m,	//PLL输出50MHz时钟
    			input clk_65m,	//PLL输出65MHz时钟
    			input clk_108m,	//PLL输出108MHz时钟
    			input clk_130m,	//PLL输出130MHz时钟
    			input rst_n,	//复位信号,低电平有效
    			output vga_r,	//VGA显示色彩R
    			output vga_g,	//VGA显示色彩G
    			output vga_b,	//VGA显示色彩B
    			output reg vga_hsy,	//VGA显示行同步信号
    			output reg vga_vsy	//VGA显示场同步信号
    		);
    
    //-----------------------------------------------------------
    wire clk;
    
    //-----------------------------------------------------------
    //`define VGA_640_480
    //`define VGA_800_600
    `define VGA_1024_768
    //`define VGA_1280_960
    //`define VGA_1280_1024
    //`define VGA_1920_1080
    
    //-----------------------------------------------------------
    `ifdef VGA_640_480
    	//VGA Timing 640*480 & 25MHz & 60Hz
    	assign clk = clk_25m;
    		
    	parameter VGA_HTT = 12'd800-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd96;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd48;//+12'd16;		//Hor Back Porch
    	parameter VGA_HVT = 12'd640;	//Hor Valid Time
    	parameter VGA_HFP = 12'd16;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd525-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd2;		//Ver Sync Time
    	parameter VGA_VBP = 12'd33;//-12'd4;		//Ver Back Porch
    	parameter VGA_VVT = 12'd480;	//Ver Valid Time
    	parameter VGA_VFP = 12'd10;		//Ver Front Porch
    	
    	parameter VGA_CORBER = 12'd80;	//8等分做Color bar显示
    `endif
    
    `ifdef VGA_800_600
    	//VGA Timing 800*600 & 50MHz & 72Hz
    	assign clk = clk_50m;
    
    	parameter VGA_HTT = 12'd1040-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd120;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd64;		//Hor Back Porch
    	parameter VGA_HVT = 12'd800;	//Hor Valid Time
    	parameter VGA_HFP = 12'd56;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd666-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd6;		//Ver Sync Time
    	parameter VGA_VBP = 12'd23;		//Ver Back Porch
    	parameter VGA_VVT = 12'd600;	//Ver Valid Time
    	parameter VGA_VFP = 12'd37;		//Ver Front Porch
    		
    	parameter VGA_CORBER = 12'd100;	//8等分做Color bar显示
    `endif
    
    `ifdef VGA_1024_768
    	//VGA Timing 1024*768 & 65MHz & 60Hz
    	assign clk = clk_65m;
    
    	parameter VGA_HTT = 12'd1344-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd136;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd160;		//Hor Back Porch
    	parameter VGA_HVT = 12'd1024;	//Hor Valid Time
    	parameter VGA_HFP = 12'd24;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd806-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd6;		//Ver Sync Time
    	parameter VGA_VBP = 12'd29;		//Ver Back Porch
    	parameter VGA_VVT = 12'd768;	//Ver Valid Time
    	parameter VGA_VFP = 12'd3;		//Ver Front Porch
    		
    	parameter VGA_CORBER = 12'd128;	//8等分做Color bar显示
    `endif
    
    `ifdef VGA_1280_960
    	//VGA Timing 1280*1024 & 108MHz & 60Hz
    	assign clk = clk_108m;
    
    	parameter VGA_HTT = 12'd1800-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd112;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd312;		//Hor Back Porch
    	parameter VGA_HVT = 12'd1280;	//Hor Valid Time
    	parameter VGA_HFP = 12'd96;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd1000-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd3;		//Ver Sync Time
    	parameter VGA_VBP = 12'd36;		//Ver Back Porch
    	parameter VGA_VVT = 12'd960;	//Ver Valid Time
    	parameter VGA_VFP = 12'd1;		//Ver Front Porch
    		
    	parameter VGA_CORBER = 12'd160;	//8等分做Color bar显示
    `endif
    
    `ifdef VGA_1280_1024
    	//VGA Timing 1280*1024 & 108MHz & 60Hz
    	assign clk = clk_108m;
    
    	parameter VGA_HTT = 12'd1688-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd112;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd248;		//Hor Back Porch
    	parameter VGA_HVT = 12'd1280;	//Hor Valid Time
    	parameter VGA_HFP = 12'd48;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd1066-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd3;		//Ver Sync Time
    	parameter VGA_VBP = 12'd38;		//Ver Back Porch
    	parameter VGA_VVT = 12'd1024;	//Ver Valid Time
    	parameter VGA_VFP = 12'd1;		//Ver Front Porch
    		
    	parameter VGA_CORBER = 12'd160;	//8等分做Color bar显示
    `endif
    
    `ifdef VGA_1920_1080
    	//VGA Timing 1920*1080 & 130MHz & 60Hz
    	assign clk = clk_130m;
    
    	parameter VGA_HTT = 12'd2000-12'd1;	//Hor Total Time
    	parameter VGA_HST = 12'd12;		//Hor Sync  Time
    	parameter VGA_HBP = 12'd40;		//Hor Back Porch
    	parameter VGA_HVT = 12'd1920;	//Hor Valid Time
    	parameter VGA_HFP = 12'd28;		//Hor Front Porch
    
    	parameter VGA_VTT = 12'd1105-12'd1;	//Ver Total Time
    	parameter VGA_VST = 12'd4;		//Ver Sync Time
    	parameter VGA_VBP = 12'd18;		//Ver Back Porch
    	parameter VGA_VVT = 12'd1080;	//Ver Valid Time
    	parameter VGA_VFP = 12'd3;		//Ver Front Porch
    		
    	parameter VGA_CORBER = 12'd240;	//8等分做Color bar显示
    `endif
    
    //-----------------------------------------------------------
    	//x和y坐标计数器
    reg[11:0] xcnt;
    reg[11:0] ycnt;
    	
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) xcnt <= 12'd0;
    	else if(xcnt >= VGA_HTT) xcnt <= 12'd0;
    	else xcnt <= xcnt+1'b1;
    
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) ycnt <= 12'd0;
    	else if(xcnt == VGA_HTT) begin
    		if(ycnt >= VGA_VTT) ycnt <= 12'd0;
    		else ycnt <= ycnt+1'b1;
    	end
    	else ;
    		
    //-----------------------------------------------------------
    	//行、场同步信号生成
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) vga_hsy <= 1'b0;
    	else if(xcnt < VGA_HST) vga_hsy <= 1'b1;
    	else vga_hsy <= 1'b0;
    	
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) vga_vsy <= 1'b0;
    	else if(ycnt < VGA_VST) vga_vsy <= 1'b1;
    	else vga_vsy <= 1'b0;	
    	
    //-----------------------------------------------------------	
    	//显示有效区域标志信号生成
    reg vga_valid;	//显示区域内,该信号高电平
    
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) vga_valid <= 1'b0;
    	else if((xcnt >= (VGA_HST+VGA_HBP)) && (xcnt < (VGA_HST+VGA_HBP+VGA_HVT))
    				&& (ycnt >= (VGA_VST+VGA_VBP)) && (ycnt < (VGA_VST+VGA_VBP+VGA_VVT)))
    		 vga_valid <= 1'b1;
    	else vga_valid <= 1'b0;
    	
    //-----------------------------------------------------------
    	//显示色彩生产逻辑
    reg vga_rdb;	//R色彩
    reg vga_gdb;	//G色彩
    reg vga_bdb;	//B色彩
    
    always @(posedge clk or negedge rst_n)
    	if(!rst_n) begin
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b0;
    	end
    	else if(xcnt == (VGA_HST+VGA_HBP)) begin	//显示第一行为绿色
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;		
    	end
    	else if(xcnt == (VGA_HST+VGA_HBP+VGA_HVT-1'b1)) begin	//显示最后一行为绿色
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;		
    	end
    	else if(ycnt == (VGA_VST+VGA_VBP)) begin	//显示第一列为绿色
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;			
    	end
    	else if(ycnt == (VGA_VST+VGA_VBP+VGA_VVT-1'b1)) begin	//显示最后一列为绿色
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;		
    	end
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER)) begin		//显示第1个Color bar
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b0;	
    	end
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER)) begin		//显示第2个Color bar
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b1;
    	end	
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第3个Color bar
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;
    	end	
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第4个Color bar
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b1;
    	end	
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第5个Color bar
    		vga_rdb <= 1'b1;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b0;	
    	end	
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第6个Color bar
    		vga_rdb <= 1'b1;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b1;	
    	end
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第7个Color bar
    		vga_rdb <= 1'b1;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b0;	
    	end
    	else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin		//显示第8个Color bar
    		vga_rdb <= 1'b1;
    		vga_gdb <= 1'b1;
    		vga_bdb <= 1'b1;	
    	end
    	else begin
    		vga_rdb <= 1'b0;
    		vga_gdb <= 1'b0;
    		vga_bdb <= 1'b0;	
    	end
    
    assign vga_r = vga_valid ? vga_rdb:1'b0;
    assign vga_g = vga_valid ? vga_gdb:1'b0;	
    assign vga_b = vga_valid ? vga_bdb:1'b0;	
    	
    endmodule

    进行了指定时钟下的时序计数并进行 I/O 的控制;

    实际情况如下:

     

     

    展开全文
  • VGA switcheroo VGA仲裁器

    2021-01-13 16:03:39
    文章目录VGA SwitcherooModes of Use“使用方式Manual switching and manual power control手动开关和手动电源控制Driver power controlAPIPublic functionsPublic structuresPublic constantsPrivate ...

    VGA Switcheroo

    vga_switcheroo is the Linux subsystem for laptop hybrid graphics. These come in two flavors:

    VGA_swicheroo 是管理多图形卡的Linux子系统,其有两个特点

    • muxed: Dual GPUs with a multiplexer chip to switch outputs between GPUs.

      混合:具有多路复用器芯片的双GPU在GPU之间切换输出

    • muxless: Dual GPUs but only one of them is connected to outputs. The other one is merely used to offload rendering, its results are copied over PCIe into the framebuffer. On Linux this is supported with DRI PRIME.

      “无混合:双GPU,但其中只有一个连接到输出。另一个仅用于卸载渲染,其结果通过PCIe复制到帧缓冲区。在Linux上,DRI PRIME支持此功能

    Hybrid graphics started to appear in the late Naughties and were initially all muxed. Newer laptops moved to a muxless architecture for cost reasons. A notable exception is the MacBook Pro which continues to use a mux. Muxes come with varying capabilities: Some switch only the panel, others can also switch external displays. Some switch all display pins at once while others can switch just the DDC lines. (To allow EDID probing for the inactive GPU.) Also, muxes are often used to cut power to the discrete GPU while it is not used.

    混合图形开始出现在晚期,最初都被混合了。出于成本原因,较新的笔记本电脑采用了无混合架构。 MacBook Pro是一个明显的例外,它继续使用多路复用器。复用器具有不同的功能:有些仅切换面板,另一些也可以切换外部显示器。有些可一次切换所有显示引脚,而另一些则只能切换DDC线。 (以允许对不活动的GPU进行EDID探测。)此外,多路复用器通常用于在不使用离散GPU时降低功耗”

    DRM drivers register GPUs with vga_switcheroo, these are henceforth called clients. The mux is called the handler. Muxless machines also register a handler to control the power state of the discrete GPU, its switchto callback is a no-op for obvious reasons. The discrete GPU is often equipped with an HDA controller for the HDMI/DP audio signal, this will also register as a client so that vga_switcheroo can take care of the correct suspend/resume order when changing the discrete GPU’s power state. In total there can thus be up to three clients: Two vga clients (GPUs) and one audio client (on the discrete GPU). The code is mostly prepared to support machines with more than two GPUs should they become available.

    DRM驱动程序用vga_switcheroo注册GPU,以后称为客户端。mux称为处理程序。Muxless机器还注册了一个处理程序来控制离散GPU的电源状态,它的switchto callback是一个no-op,原因很明显。离散GPU通常为HDMI/DP音频信号配备一个HDA控制器,该控制器还将注册为客户端,以便在更改离散GPU的电源状态时,vga_switcheroo可以处理正确的挂起/恢复顺序。因此,总共可以有三个客户机:两个vga客户机(GPU)和一个音频客户机(在离散的GPU上)。如果有超过两个gpu的机器可用,代码主要是用来支持它们的。

    The GPU to which the outputs are currently switched is called the active client in vga_switcheroo parlance. The GPU not in use is the inactive client. When the inactive client’s DRM driver is loaded, it will be unable to probe the panel’s EDID and hence depends on VBIOS to provide its display modes. If the VBIOS modes are bogus or if there is no VBIOS at all (which is common on the MacBook Pro), a client may alternatively request that the DDC lines are temporarily switched to it, provided that the handler supports this. Switching only the DDC lines and not the entire output avoids unnecessary flickering.

    用vga-switchero的说法,输出当前切换到的GPU称为活动客户机。未使用的GPU是非活动客户端。当加载非活动客户端的DRM驱动程序时,它将无法探测面板的EDID,因此依赖VBIOS提供其显示模式。如果VBIOS模式是假的,或者根本没有VBIOS(这在MacBook Pro上很常见),客户机可以选择请求将DDC线路临时切换到它,前提是处理程序支持这种方式。只切换DDC线路而不是整个输出避免不必要的闪烁

    Modes of Use“使用方式

    Manual switching and manual power control手动开关和手动电源控制

    In this mode of use, the file /sys/kernel/debug/vgaswitcheroo/switch can be read to retrieve the current vga_switcheroo state and commands can be written to it to change the state. The file appears as soon as two GPU drivers and one handler have registered with vga_switcheroo. The following commands are understood:

    在这种使用模式下,可以读取文件/sys/kernel/debug/vga switcheroo/switch来检索当前的vga_switcheroo状态,并可以向其写入命令来更改状态。当两个GPU驱动程序和一个处理程序注册到vga_switcheroo后,文件就会出现。可以理解以下命令

    IGD: Integrated Graphic Device (mostly Intel)
    DIS: denotes DIScrete graphic device (nVidia or ATI)
    OFF - power off the unused device
    ON - power on the unused device
    DIGD - delayed switch to integrated device (at next X startup)
    DDIS - delayed switch to discrete device at next X startup)
    IGD - immediate switch to integrated device
    DIS - immediate switch to discrete device
    MIGD - mux switch to integrated device (if I am right, at next reboot)
    MDIS - mux switch to discrete device (if I am right, at next reboot)

    • OFF: Power off the device not in use.关闭不使用的设备

    • ON: Power on the device not in use.打开未使用的设备的电源

    • IGD: Switch to the integrated graphics device. Power on the integrated GPU if necessary, power off the discrete GPU. Prerequisite is that no user space processes (e.g. Xorg, alsactl) have opened device files of the GPUs or the audio client. If the switch fails, the user may invoke lsof(8) or fuser(1) on /dev/dri/ and /dev/snd/controlC1 to identify processes blocking the switch.

      切换到集成图形设备。必要时打开集成GPU,关闭离散GPU。先决条件是没有用户空间进程(例如Xorg、alsactl)打开gpu或音频客户端的设备文件。如果交换机出现故障,用户可以调用/dev/dri/和/dev/snd/controlC1上的lsof(8)或fuser(1)来识别阻塞交换机的进程。

    • DIS: Switch to the discrete graphics device.切换到独显设备

    • DIGD: Delayed switch to the integrated graphics device. This will perform the switch once the last user space process has closed the device files of the GPUs and the audio client.延迟切换到集成图形设备。这将在最后一个用户空间进程关闭GPU和音频客户端的设备文件后执行切换

    • DDIS: Delayed switch to the discrete graphics device.延迟切换到独显图形设备

    • MIGD: Mux-only switch to the integrated graphics device. Does not remap console or change the power state of either gpu. If the integrated GPU is currently off, the screen will turn black. If it is on, the screen will show whatever happens to be in VRAM. Either way, the user has to blindly enter the command to switch back.

      Mux只能切换到集成图形设备。不重新映射控制台或更改任一gpu的电源状态。如果集成GPU当前处于关闭状态,则屏幕将变为黑色。如果打开,屏幕将显示VRAM中发生的任何情况。不管怎样,用户都必须盲目地输入命令才能切换回原来的状态

    • MDIS: Mux-only switch to the discrete graphics device.Mux仅切换到独显图形设备

    For GPUs whose power state is controlled by the driver’s runtime pm, the ON and OFF commands are a no-op (see next section).对于电源状态由驱动程序运行时pm控制的GPU,开和关命令是noop的禁止操作

    For muxless machines, the IGD/DIS, DIGD/DDIS and MIGD/MDIS commands should not be used.

    对于单显示的驱动.不应使用IGD/DIS、DIGD/DDIS和MIGD/MDIS命令

    Driver power control

    In this mode of use, the discrete GPU automatically powers up and down at the discretion of the driver’s runtime pm. On muxed machines, the user may still influence the muxer state by way of the debugfs interface, however the ON and OFF commands become a no-op for the discrete GPU.

    使用这种模式.独显可以在判断驱动的pm的后自动控制power的up和down,在混合模式,user仍然可以通过debugfs接口影响混合模式的状态,但是独显的ON和OFF操作被禁止

    This mode is the default on Nvidia HybridPower/Optimus and ATI PowerXpress. Specifying nouveau.runpm=0, radeon.runpm=0 or amdgpu.runpm=0 on the kernel command line disables it.

    此模式是Nvidia HybridPower/Optimus和ATI PowerXpress的默认模式。在内核命令行上指定nouveau.runpm=0、radeon.runpm=0或amdgpu.runpm=0将禁用它。

    After the GPU has been suspended, the handler needs to be called to cut power to the GPU. Likewise it needs to reinstate power before the GPU can resume. This is achieved by vga_switcheroo_init_domain_pm_ops(), which augments the GPU’s suspend/resume functions by the requisite calls to the handler.

    GPU被挂起后.需要调用切断电源的处理程序.同样,在GPU恢复之前,要提前做供电处理.这些可以通过vga_switcheroo_init_domain_pm_ops()操作上/下电

    When the audio device resumes, the GPU needs to be woken. This is achieved by a PCI quirk which calls device_link_add() to declare a dependency on the GPU. That way, the GPU is kept awake whenever and as long as the audio device is in use.

    当音频设备恢复时,需要唤醒GPU。这是通过一个PCI quirk实现的,它调用device_link_add()来声明对GPU的依赖性。这样,只要音频设备在使用中,GPU就保持清醒

    On muxed machines, if the mux is initially switched to the discrete GPU, the user ends up with a black screen when the GPU powers down after boot. As a workaround, the mux is forced to the integrated GPU on runtime suspend, cf. https://bugs.freedesktop.org/show_bug.cgi?id=75917

    在muxed上,如果mux最初被切换到独显GPU,当GPU在启动后关机时,用户最终会看到一个黑屏。作为一种解决方法,mux在运行时挂起时被强制到集成GPU

    API

    Public functions

    Parameters

    • const struct vga_switcheroo_handler * handler

      handler callbacks

    • enum vga_switcheroo_handler_flags_t handler_flags

      handler flags

    Description

    Register handler. Enable vga_switcheroo if two vga clients have already registered.

    Return

    0 on success, -EINVAL if a handler was already registered.

    • void vga_switcheroo_unregister_handler(void)

      unregister handler

    Parameters

    • void

      no arguments

    Description

    Unregister handler. Disable vga_switcheroo.

    Parameters

    • void

      no arguments

    Description

    Helper for clients to obtain the handler flags bitmask.

    Return

    Handler flags. A value of 0 means that no handler is registered or that the handler has no special capabilities.

    • int vga_switcheroo_register_client(struct pci_dev * pdev, const struct vga_switcheroo_client_ops * ops, bool driver_power_control)

      register vga client

    Parameters

    • struct pci_dev * pdev

      client pci device

    • const struct vga_switcheroo_client_ops * ops

      client callbacks

    • bool driver_power_control

      whether power state is controlled by the driver’s runtime pm

    Description

    Register vga client (GPU). Enable vga_switcheroo if another GPU and a handler have already registered. The power state of the client is assumed to be ON. Beforehand, vga_switcheroo_client_probe_defer() shall be called to ensure that all prerequisites are met.

    Return

    0 on success, -ENOMEM on memory allocation error.

    • int vga_switcheroo_register_audio_client(struct pci_dev * pdev, const struct vga_switcheroo_client_ops * ops, struct pci_dev * vga_dev)

      register audio client

    Parameters

    • struct pci_dev * pdev

      client pci device

    • const struct vga_switcheroo_client_ops * ops

      client callbacks

    • struct pci_dev * vga_dev

      pci device which is bound to current audio client

    Description

    Register audio client (audio device on a GPU). The client is assumed to use runtime PM. Beforehand, vga_switcheroo_client_probe_defer() shall be called to ensure that all prerequisites are met.

    Return

    0 on success, -ENOMEM on memory allocation error, -EINVAL on getting client id error.

    • bool vga_switcheroo_client_probe_defer(struct pci_dev * pdev)

      whether to defer probing a given client

    Parameters

    • struct pci_dev * pdev

      client pci device

    Description

    Determine whether any prerequisites are not fulfilled to probe a given client. Drivers shall invoke this early on in their ->probe callback and return -EPROBE_DEFER if it evaluates to true. Thou shalt not register the client ere thou hast called this.

    Return

    true if probing should be deferred, otherwise false.

    • enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev * pdev)

      obtain power state of a given client

    Parameters

    • struct pci_dev * pdev

      client pci device

    Description

    Obtain power state of a given client as seen from vga_switcheroo. The function is only called from hda_intel.c.

    Return

    Power state.

    • void vga_switcheroo_unregister_client(struct pci_dev * pdev)

      unregister client

    Parameters

    • struct pci_dev * pdev

      client pci device

    Description

    Unregister client. Disable vga_switcheroo if this is a vga client (GPU).

    • void vga_switcheroo_client_fb_set(struct pci_dev * pdev, struct fb_info * info)

      set framebuffer of a given client

    Parameters

    • struct pci_dev * pdev

      client pci device

    • struct fb_info * info

      framebuffer

    Description

    Set framebuffer of a given client. The console will be remapped to this on switching.

    • int vga_switcheroo_lock_ddc(struct pci_dev * pdev)

      temporarily switch DDC lines to a given client

    Parameters

    • struct pci_dev * pdev

      client pci device

    Description

    Temporarily switch DDC lines to the client identified by pdev (but leave the outputs otherwise switched to where they are). This allows the inactive client to probe EDID. The DDC lines must afterwards be switched back by calling vga_switcheroo_unlock_ddc(), even if this function returns an error.

    Return

    Previous DDC owner on success or a negative int on error. Specifically, -ENODEV if no handler has registered or if the handler does not support switching the DDC lines. Also, a negative value returned by the handler is propagated back to the caller. The return value has merely an informational purpose for any caller which might be interested in it. It is acceptable to ignore the return value and simply rely on the result of the subsequent EDID probe, which will be NULL if DDC switching failed.

    • int vga_switcheroo_unlock_ddc(struct pci_dev * pdev)

      switch DDC lines back to previous owner

    Parameters

    • struct pci_dev * pdev

      client pci device

    Description

    Switch DDC lines back to the previous owner after calling vga_switcheroo_lock_ddc(). This must be called even if vga_switcheroo_lock_ddc() returned an error.

    Return

    Previous DDC owner on success (i.e. the client identifier of pdev) or a negative int on error. Specifically, -ENODEV if no handler has registered or if the handler does not support switching the DDC lines. Also, a negative value returned by the handler is propagated back to the caller. Finally, invoking this function without calling vga_switcheroo_lock_ddc() first is not allowed and will result in -EINVAL.

    • int vga_switcheroo_process_delayed_switch(void)

      helper for delayed switching

    Parameters

    • void

      no arguments

    Description

    Process a delayed switch if one is pending. DRM drivers should call this from their ->lastclose callback.

    Return

    0 on success. -EINVAL if no delayed switch is pending, if the client has unregistered in the meantime or if there are other clients blocking the switch. If the actual switch fails, an error is reported and 0 is returned.

    • int vga_switcheroo_init_domain_pm_ops(struct device * dev, struct dev_pm_domain * domain)

      helper for driver power control

    Parameters

    • struct device * dev

      vga client device

    • struct dev_pm_domain * domain

      power domain

    Description

    Helper for GPUs whose power state is controlled by the driver’s runtime pm. After the GPU has been suspended, the handler needs to be called to cut power to the GPU. Likewise it needs to reinstate power before the GPU can resume. To this end, this helper augments the suspend/resume functions by the requisite calls to the handler. It needs only be called on platforms where the power switch is separate to the device being powered down.

    Public structures

    • struct vga_switcheroo_handler

      handler callbacks

    Definition

    struct vga_switcheroo_handler {
      int (*init)(void);
      int (*switchto)(enum vga_switcheroo_client_id id);
      int (*switch_ddc)(enum vga_switcheroo_client_id id);
      int (*power_state)(enum vga_switcheroo_client_id id, enum vga_switcheroo_state state);
      enum vga_switcheroo_client_id (*get_client_id)(struct pci_dev *pdev);
    };
    

    Members

    • init

      initialize handler. Optional. This gets called when vga_switcheroo is enabled, i.e. when two vga clients have registered. It allows the handler to perform some delayed initialization that depends on the existence of the vga clients. Currently only the radeon and amdgpu drivers use this. The return value is ignored

    • switchto

      switch outputs to given client. Mandatory. For muxless machines this should be a no-op. Returning 0 denotes success, anything else failure (in which case the switch is aborted)

    • switch_ddc

      switch DDC lines to given client. Optional. Should return the previous DDC owner on success or a negative int on failure

    • power_state

      cut or reinstate power of given client. Optional. The return value is ignored

    • get_client_id

      determine if given pci device is integrated or discrete GPU. Mandatory

    Description

    Handler callbacks. The multiplexer itself. The switchto and get_client_id methods are mandatory, all others may be set to NULL.

    • struct vga_switcheroo_client_ops

      client callbacks

    Definition

    struct vga_switcheroo_client_ops {
      void (*set_gpu_state)(struct pci_dev *dev, enum vga_switcheroo_state);
      void (*reprobe)(struct pci_dev *dev);
      bool (*can_switch)(struct pci_dev *dev);
      void (*gpu_bound)(struct pci_dev *dev, enum vga_switcheroo_client_id);
    };
    

    Members

    • set_gpu_state

      do the equivalent of suspend/resume for the card. Mandatory. This should not cut power to the discrete GPU, which is the job of the handler

    • reprobe

      poll outputs. Optional. This gets called after waking the GPU and switching the outputs to it

    • can_switch

      check if the device is in a position to switch now. Mandatory. The client should return false if a user space process has one of its device files open

    • gpu_bound

      notify the client id to audio client when the GPU is bound.

    Description

    Client callbacks. A client can be either a GPU or an audio device on a GPU. The set_gpu_state and can_switch methods are mandatory, reprobe may be set to NULL. For audio clients, the reprobe member is bogus. OTOH, gpu_bound is only for audio clients, and not used for GPU clients.

    Public constants

    • enum vga_switcheroo_handler_flags_t

      handler flags bitmask

    Constants

    • VGA_SWITCHEROO_CAN_SWITCH_DDC

      whether the handler is able to switch the DDC lines separately. This signals to clients that they should call drm_get_edid_switcheroo() to probe the EDID

    • VGA_SWITCHEROO_NEEDS_EDP_CONFIG

      whether the handler is unable to switch the AUX channel separately. This signals to clients that the active GPU needs to train the link and communicate the link parameters to the inactive GPU (mediated by vga_switcheroo). The inactive GPU may then skip the AUX handshake and set up its output with these pre-calibrated values (DisplayPort specification v1.1a, section 2.5.3.3)

    Description

    Handler flags bitmask. Used by handlers to declare their capabilities upon registering with vga_switcheroo.

    • enum vga_switcheroo_client_id

      client identifier

    Constants

    • VGA_SWITCHEROO_UNKNOWN_ID

      initial identifier assigned to vga clients. Determining the id requires the handler, so GPUs are given their true id in a delayed fashion in vga_switcheroo_enable()

    • VGA_SWITCHEROO_IGD

      integrated graphics device

    • VGA_SWITCHEROO_DIS

      discrete graphics device

    • VGA_SWITCHEROO_MAX_CLIENTS

      currently no more than two GPUs are supported

    Description

    Client identifier. Audio clients use the same identifier & 0x100.

    • enum vga_switcheroo_state

      client power state

    Constants

    • VGA_SWITCHEROO_OFF

      off

    • VGA_SWITCHEROO_ON

      on

    • VGA_SWITCHEROO_NOT_FOUND

      client has not registered with vga_switcheroo. Only used in vga_switcheroo_get_client_state() which in turn is only called from hda_intel.c

    Description

    Client power state.

    Private structures

    • struct vgasr_priv

      vga_switcheroo private data

    Definition

    struct vgasr_priv {
      bool active;
      bool delayed_switch_active;
      enum vga_switcheroo_client_id delayed_client_id;
      struct dentry *debugfs_root;
      int registered_clients;
      struct list_head clients;
      const struct vga_switcheroo_handler *handler;
      enum vga_switcheroo_handler_flags_t handler_flags;
      struct mutex mux_hw_lock;
      int old_ddc_owner;
    };
    

    Members

    • active

      whether vga_switcheroo is enabled. Prerequisite is the registration of two GPUs and a handler

    • delayed_switch_active

      whether a delayed switch is pending

    • delayed_client_id

      client to which a delayed switch is pending

    • debugfs_root

      directory for vga_switcheroo debugfs interface

    • registered_clients

      number of registered GPUs (counting only vga clients, not audio clients)

    • clients

      list of registered clients

    • handler

      registered handler

    • handler_flags

      flags of registered handler

    • mux_hw_lock

      protects mux state (in particular while DDC lines are temporarily switched)

    • old_ddc_owner

      client to which DDC lines will be switched back on unlock

    Description

    vga_switcheroo private data. Currently only one vga_switcheroo instance per system is supported.

    • struct vga_switcheroo_client

      registered client

    Definition

    struct vga_switcheroo_client {
      struct pci_dev *pdev;
      struct fb_info *fb_info;
      enum vga_switcheroo_state pwr_state;
      const struct vga_switcheroo_client_ops *ops;
      enum vga_switcheroo_client_id id;
      bool active;
      bool driver_power_control;
      struct list_head list;
      struct pci_dev *vga_dev;
    };
    

    Members

    • pdev

      client pci device

    • fb_info

      framebuffer to which console is remapped on switching

    • pwr_state

      current power state if manual power control is used. For driver power control, call vga_switcheroo_pwr_state().

    • ops

      client callbacks

    • id

      client identifier. Determining the id requires the handler, so gpus are initially assigned VGA_SWITCHEROO_UNKNOWN_ID and later given their true id in vga_switcheroo_enable()

    • active

      whether the outputs are currently switched to this client

    • driver_power_control

      whether power state is controlled by the driver’s runtime pm. If true, writing ON and OFF to the vga_switcheroo debugfs interface is a no-op so as not to interfere with runtime pm

    • list

      client list

    • vga_dev

      pci device, indicate which GPU is bound to current audio client

    Description

    Registered client. A client can be either a GPU or an audio device on a GPU. For audio clients, the fb_info and active members are bogus. For GPU clients, the vga_dev is bogus.

    Handlers

    apple-gmux Handler

    gmux is a microcontroller built into the MacBook Pro to support dual GPUs: A Lattice XP2 on pre-retinas, a Renesas R4F2113 on retinas.

    (The MacPro6,1 2013 also has a gmux, however it is unclear why since it has dual GPUs but no built-in display.)

    gmux is connected to the LPC bus of the southbridge. Its I/O ports are accessed differently depending on the microcontroller: Driver functions to access a pre-retina gmux are infixed _pio_, those for a retina gmux are infixed _index_.

    gmux is also connected to a GPIO pin of the southbridge and thereby is able to trigger an ACPI GPE. On the MBP5 2008/09 it’s GPIO pin 22 of the Nvidia MCP79, on all following generations it’s GPIO pin 6 of the Intel PCH. The GPE merely signals that an interrupt occurred, the actual type of event is identified by reading a gmux register.

    Graphics mux

    On pre-retinas, the LVDS outputs of both GPUs feed into gmux which muxes either of them to the panel. One of the tricks gmux has up its sleeve is to lengthen the blanking interval of its output during a switch to synchronize it with the GPU switched to. This allows for a flicker-free switch that is imperceptible by the user (US 8,687,007 B2).

    On retinas, muxing is no longer done by gmux itself, but by a separate chip which is controlled by gmux. The chip is triple sourced, it is either an NXP CBTL06142, TI HD3SS212 or Pericom PI3VDP12412. The panel is driven with eDP instead of LVDS since the pixel clock required for retina resolution exceeds LVDS’ limits.

    Pre-retinas are able to switch the panel’s DDC pins separately. This is handled by a TI SN74LV4066A which is controlled by gmux. The inactive GPU can thus probe the panel’s EDID without switching over the entire panel. Retinas lack this functionality as the chips used for eDP muxing are incapable of switching the AUX channel separately (see the linked data sheets, Pericom would be capable but this is unused). However the retina panel has the NO_AUX_HANDSHAKE_LINK_TRAINING bit set in its DPCD, allowing the inactive GPU to skip the AUX handshake and set up the output with link parameters pre-calibrated by the active GPU.

    The external DP port is only fully switchable on the first two unibody MacBook Pro generations, MBP5 2008/09 and MBP6 2010. This is done by an NXP CBTL06141 which is controlled by gmux. It’s the predecessor of the eDP mux on retinas, the difference being support for 2.7 versus 5.4 Gbit/s.

    The following MacBook Pro generations replaced the external DP port with a combined DP/Thunderbolt port and lost the ability to switch it between GPUs, connecting it either to the discrete GPU or the Thunderbolt controller. Oddly enough, while the full port is no longer switchable, AUX and HPD are still switchable by way of an NXP CBTL03062 (on pre-retinas MBP8 2011 and MBP9 2012) or two TI TS3DS10224 (on retinas) under the control of gmux. Since the integrated GPU is missing the main link, external displays appear to it as phantoms which fail to link-train.

    gmux receives the HPD signal of all display connectors and sends an interrupt on hotplug. On generations which cannot switch external ports, the discrete GPU can then be woken to drive the newly connected display. The ability to switch AUX on these generations could be used to improve reliability of hotplug detection by having the integrated GPU poll the ports while the discrete GPU is asleep, but currently we do not make use of this feature.

    Our switching policy for the external port is that on those generations which are able to switch it fully, the port is switched together with the panel when IGD / DIS commands are issued to vga_switcheroo. It is thus possible to drive e.g. a beamer on battery power with the integrated GPU. The user may manually switch to the discrete GPU if more performance is needed.

    On all newer generations, the external port can only be driven by the discrete GPU. If a display is plugged in while the panel is switched to the integrated GPU, both GPUs will be in use for maximum performance. To decrease power consumption, the user may manually switch to the discrete GPU, thereby suspending the integrated GPU.

    gmux’ initial switch state on bootup is user configurable via the EFI variable gpu-power-prefs-fa4ce28d-b62f-4c99-9cc3-6815686e30f9 (5th byte, 1 = IGD, 0 = DIS). Based on this setting, the EFI firmware tells gmux to switch the panel and the external DP connector and allocates a framebuffer for the selected GPU.

    Power control

    gmux is able to cut power to the discrete GPU. It automatically takes care of the correct sequence to tear down and bring up the power rails for core voltage, VRAM and PCIe.

    Backlight control

    On single GPU MacBooks, the PWM signal for the backlight is generated by the GPU. On dual GPU MacBook Pros by contrast, either GPU may be suspended to conserve energy. Hence the PWM signal needs to be generated by a separate backlight driver which is controlled by gmux. The earliest generation MBP5 2008/09 uses a TI LP8543 backlight driver. All newer models use a TI LP8545.

    Public functions

    • bool apple_gmux_present(void)

      detect if gmux is built into the machine

    Parameters

    • void

      no arguments

    Description

    Drivers may use this to activate quirks specific to dual GPU MacBook Pros and Mac Pros, e.g. for deferred probing, runtime pm and backlight.

    Return

    true if gmux is present and the kernel was configured with CONFIG_APPLE_GMUX, false otherwise.

    展开全文
  • 1 Features ... VGA Output  Up to 1920x1200@60Hz supported  DisplayPort Input  Compliant with VESA DisplayPort 1.2 for  1.62Gbps/2.7Gbps  Support DisplayPort 1/2 lanes  1Mbps AUX
    1 Features
       VGA Output
        Up to 1920x1200@60Hz supported
        DisplayPort Input
        Compliant with VESA DisplayPort 1.2 for
        1.62Gbps/2.7Gbps
        Support DisplayPort 1/2 lanes
       1Mbps AUX channel
        Adaptive equalization
        Support Hot-Plug Detect
        Slave IIC updating
        Master IIC for VGA
      Clock
        Refless clock system
      Misc
        On-chip 3.3V to 1.2V regulator
        Built-in video test pattern
      Power
        3.3V core supply
       1.2V core generated by internal regulator
       3.3V/2.5V IO supply
       Power consumption
      @ 1920*1200*24bit*60Hz ~ 330mW
       Deep-sleep mode power <1mW
      Package
       QFN-32 (4mm x 4mm) package
       RoHS Compliant

    2 Block Diagram


    3 General Description
        NCS8822 is a low-power DisplayPort-to-VGA converter.
       The NCS8822 integrates a DP1.2 compliant receiver and a high-speed triple-channel video DAC.For DP1.2 input NCS8822 supports 1-lane/2-lane, also support lane swap function.
        For VGA output NCS8822 Maximum support to WUXGA (1920*1200) and above at 60Hz frame rate.
        NCS8822 provides high picture quality. All the functions pack into a small 4mm*4mmQFN32 package which saves the precious space in mobile devices.
    4 Pin Diagram


    5 Pin Description

    展开全文
  • VGA的标准时序

    千次阅读 2017-01-13 10:27:06
    VGA Timings The following table lists timing values for several popular resolutions. Format Pixel Clock (MHz) Horizontal (in Pixels) Vertical (in Lines) Active Video Front Porch

    VGA Timings

    The following table lists timing values for several popular resolutions.

    FormatPixel Clock
    (MHz)
    Horizontal (in Pixels)Vertical (in Lines)
    Active
    Video
    Front
    Porch
    Sync
    Pulse
    Back
    Porch
    Active
    Video
    Front
    Porch
    Sync
    Pulse
    Back
    Porch
    640x480, 60Hz 25.175 640 16 96 48 480 11 2 31
    640x480, 72Hz 31.500 640 24 40 128 480 9 3 28
    640x480, 75Hz 31.500 640 16 96 48 480 11 2 32
    640x480, 85Hz 36.000 640 32 48 112 480 1 3 25
    800x600, 56Hz 38.100 800 32 128 128 600 1 4 14
    800x600, 60Hz 40.000 800 40 128 88 600 1 4 23
    800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
    800x600, 75Hz 49.500 800 16 80 160 600 1 2 21
    800x600, 85Hz 56.250 800 32 64 152 600 1 3 27
    1024x768, 60Hz 65.000 1024 24 136 160 768 3 6 29
    1024x768, 70Hz 75.000 1024 24 136 144 768 3 6 29
    1024x768, 75Hz 78.750 1024 16 96 176 768 1 3 28
    1024x768, 85Hz 94.500 1024 48 96 208 768 1 3 36
    Source: Rick Ballantyne, Xilinx Inc.   TABLE 1 VGA CORE VIDEO MODE


    Mode

    Type

    Res.

    Colors

    Vert.

    Horz.

    Pix Clk

    SM and SXGA MODES

    0, 1

    A/N

    320 x 200

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    2, 3

    A/N

    640 x 200

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    0*, 1*

    A/N

    320 x 350

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    2*, 3*

    A/N

    640 x 350

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    0+, 1+

    A/N

    320 x 350

    16

    70 Hz

    31.778 KHz

    28.322 MHz

    2+, 3+

    A/N

    640 x 350

    16

    70 Hz

    31.778 KHz

    28.322 MHz

    4, 5

    APA

    320 x 200

    4

    70 Hz

    31.778 KHz

    25.175 MHz

    6

    APA

    640 x 200

    2

    70 Hz

    31.778 KHz

    25.175 MHz

    7

    A/N

    720 x 350

    Mono

    70 Hz

    31.778 KHz

    28.322 MHz

    7+

    A/N

    720 x 400

    Mono

    70 Hz

    31.778 KHz

    28.322 MHz

    D

    APA

    320 x 200

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    E

    APA

    640 x 200

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    F

    APA

    640 x 350

    Mono

    70 Hz

    31.778 KHz

    25.175 MHz

    10

    APA

    640 x 350

    16

    70 Hz

    31.778 KHz

    25.175 MHz

    11

    APA

    640 x 480

    2

    60Hz

    31.778 KHz

    25.175 MHz

    12

    APA

    640 x 480

    16

    60Hz

    31.778 KHz

    25.175 MHz

    13

    APA

    320 x 200

    256

    70 Hz

    31.778 KHz

    25.175 MHz

    SXGA MODES

    101

    APA

    640x480

    256

    85 Hz

    43.3 KHz

    36.00 MHz

    102

    APA

    800 x 600

    16

    85 Hz

    53.7 KHz

    56.25 MHz

    103

    APA

    800 x 600

    256

    85 Hz

    53.7 KHz

    56.25 MHz

    104

    APA

    1024 x 768

    16

    85 Hz

    68.7 KHz

    94.5 MHz

    105

    APA

    1024 x 768

    256

    85 Hz

    68.7 KHz

    94.5 MHz

    106

    APA

    1280 x 1024

    16

    85 Hz

    91.1 KHz

    157.5 MHz

    107

    APA

    1280 x 1024

    256

    85 Hz

    91.1 KHz

    157.5 MHz

    114

    APA

    800 x 600

    64K

    85 Hz

    53.7 KHz

    56.25 MHz

    115

    APA

    800 x 600

    16.8 M

    85 Hz

    53.7 KHz

    56.25 MHz

    117

    APA

    1024 x 768

    64K

    85 Hz

    68.7 KHz

    94.5 MHz

    118

    APA

    1024 x 768

    16.8 M

    85 Hz

    68.7 KHz

    94.5 MHz

    11A

    APA

    1280 x 1024

    64K

    85 Hz

    91.1 KHz

    157.5 MHz

    11B

    APA

    1280 x 1024

    16.8 M

    85 Hz

    91.1 KHz

    157.5 MHz

    Note: SM Modes 0-13 only


    As with RS-232, the standard for VGA video is that there are lots of standards. Every manufacturer seems to list different timings in the manuals for their monitors. The values given in the table above are not particularly critical. On a CRT monitor, the lengths of the front and back porches control the position of the image on the display. If the image appears offset to the right or left, or up or down, try adjusting the front and back porch values for the corresponding direction (or use the image position adjustments on the monitor, which accomplish the same thing).

    Mode name   Pixel syn c back a ctive front whole line Lines line sync sync back active active front front whole frame whole frame
        clock pul se porch time porch period Total width pulse pulse porch time time porch porch period period
        (MHz) (us) (pix) (pix) (pix) (pix) (pix)   (us) (us) (lin) (us)(lin) (us) (lin) (us) (lin) (us) (lin)
                                           
    VGA 640x480 60Hz 25.175 3.81 96 45 646 13 800 525 31.78 63 2 953 30 15382 484 285 9 16683 525
    VGA 640x480 72Hz 31.5 1.27 40 125 646 21 832 520 26.41 79 3 686 26 12782 484 184 7 13735 520
    VGA 720x400 70Hz 28.322 3.81 108 51 726 15 900 449 31.78 63 2 1016 32 12839 404 349 11 14268 449
    VGA 720x350 70Hz 28.322 3.81 108 51 726 15 900 449 31.78 63 2 1811 57 11250 354 1144 36 14268 449
    VGA 800x600 56Hz 36.000 2 72 125 806 21 1024 625 28.44 56 1 568 20 17177 604   -1* 17775 625
    VGA 800x600 60Hz 40 3.2 128 85 806 37 1056 628 26.40 106 4 554 21 15945 604   -1* 16579 628
    VGA 800x600 72Hz 50.000 2.4 120 61 806 53 1040 666 20.80 125 6 436 21 12563 604 728 35 13853 666
    IBM 640x480 75Hz 31.05 3.05 96 45 646 13 800 525 25.397 51 2 761 30 12292 484 228 9 13333 525
    MAC 640x480 66Hz 30.240 2.11 64 93 646 61 864 525 28.57 86 3 1057 37 13827 484 28 1 14999 525
    • Active area is actually an active area added with 6 overscan border pixels (in some other VGA timing tables those border pixels are included in back and front porch)

      640x480@60 25.2 640 656 752 800 480 490 492 525 -vsync -hsync
      800x600@56 36.0 800 824 896 1024 600 601 603 625 +hsync +vsync
      800x600@60 40.0 800 840 968 1056 600 601 605 628 +hsync +vsync
      1024x768@60 65.0 1024 1048 1184 1344 768 771 777 806 -vsync -hsync
      1280x960@60 102.1 1280 1360 1496 1712 960 961 964 994 -hsync +vsync
      1280x1024@60 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync
      1400x1050@60 122.61 1400 1488 1640 1880 1050 1051 1054 1087 -hsync +vsync
      1600x1200@60 162.0 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    640x350 @ 85Hz (VESA) hsync: 37.9kHz 640x350 31.5 640 672 736 832 350 382 385 445 +hsync -vsync
    640x400 @ 85Hz (VESA) hsync: 37.9kHz 640x400 31.5 640 672 736 832 400 401 404 445 -hsync +vsync
    720x400 @ 85Hz (VESA) hsync: 37.9kHz 720x400 35.5 720 756 828 936 400 401 404 446 -hsync +vsync
    640x480 @ 60Hz (Industry standard) hsync: 31.5kHz 640x480 25.2 640 656 752 800 480 490 492 525 -hsync -vsync
    640x480 @ 72Hz (VESA) hsync: 37.9kHz 640x480 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
    640x480 @ 75Hz (VESA) hsync: 37.5kHz 640x480 31.5 640 656 720 840 480 481 484 500 -hsync -vsync
    640x480 @ 85Hz (VESA) hsync: 43.3kHz 640x480 36.0 640 696 752 832 480 481 484 509 -hsync -vsync
    800x600 @ 56Hz (VESA) hsync: 35.2kHz 800x600 36.0 800 824 896 1024 600 601 603 625 +hsync +vsync
    800x600 @ 60Hz (VESA) hsync: 37.9kHz 800x600 40.0 800 840 968 1056 600 601 605 628 +hsync +vsync
    800x600 @ 72Hz (VESA) hsync: 48.1kHz 800x600 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync
    800x600 @ 75Hz (VESA) hsync: 46.9kHz 800x600 49.5 800 816 896 1056 600 601 604 625 +hsync +vsync
    800x600 @ 85Hz (VESA) hsync: 53.7kHz 800x600 56.3 800 832 896 1048 600 601 604 631 +hsync +vsync
    1024x768i @ 43Hz (industry standard) hsync: 35.5kHz 1024x768 44.9 1024 1032 1208 1264 768 768 776 817 +hsync +vsync Interlace
    1024x768 @ 60Hz (VESA) hsync: 48.4kHz 1024x768 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync
    1024x768 @ 70Hz (VESA) hsync: 56.5kHz 1024x768 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync
    1024x768 @ 75Hz (VESA) hsync: 60.0kHz 1024x768 78.8 1024 1040 1136 1312 768 769 772 800 +hsync +vsync
    1024x768 @ 85Hz (VESA) hsync: 68.7kHz 1024x768 94.5 1024 1072 1168 1376 768 769 772 808 +hsync +vsync
    1152x864 @ 75Hz (VESA) hsync: 67.5kHz 1152x864 108.0 1152 1216 1344 1600 864 865 868 900 +hsync +vsync
    1280x960 @ 60Hz (VESA) hsync: 60.0kHz 1280x960 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync
    1280x960 @ 85Hz (VESA) hsync: 85.9kHz 1280x960 148.5 1280 1344 1504 1728 960 961 964 1011 +hsync +vsync
    1280x1024 @ 60Hz (VESA) hsync: 64.0kHz 1280x1024 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync
    1280x1024 @ 75Hz (VESA) hsync: 80.0kHz 1280x1024 135.0 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync
    1280x1024 @ 85Hz (VESA) hsync: 91.1kHz 1280x1024 157.5 1280 1344 1504 1728 1024 1025 1028 1072 +hsync +vsync
    1600x1200 @ 60Hz (VESA) hsync: 75.0kHz 1600x1200 162.0 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    1600x1200 @ 65Hz (VESA) hsync: 81.3kHz 1600x1200 175.5 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    1600x1200 @ 70Hz (VESA) hsync: 87.5kHz 1600x1200 189.0 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    1600x1200 @ 75Hz (VESA) hsync: 93.8kHz 1600x1200 202.5 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    1600x1200 @ 85Hz (VESA) hsync: 106.3kHz 1600x1200 229.5 1600 1664 1856 2160 1200 1201 1204 1250 +hsync +vsync
    1792x1344 @ 60Hz (VESA) hsync: 83.6kHz 1792x1344 204.8 1792 1920 2120 2448 1344 1345 1348 1394 -hsync +vsync
    1792x1344 @ 75Hz (VESA) hsync: 106.3kHz 1792x1344 261.0 1792 1888 2104 2456 1344 1345 1348 1417 -hsync +vsync
    1856x1392 @ 60Hz (VESA) hsync: 86.3kHz 1856x1392 218.3 1856 1952 2176 2528 1392 1393 1396 1439 -hsync +vsync
    1856x1392 @ 75Hz (VESA) hsync: 112.5kHz 1856x1392 288.0 1856 1984 2208 2560 1392 1393 1396 1500 -hsync +vsync
    1920x1440 @ 60Hz (VESA) hsync: 90.0kHz 1920x1440 234.0 1920 2048 2256 2600 1440 1441 1444 1500 -hsync +vsync
    1920x1440 @ 75Hz (VESA) hsync: 112.5kHz 1920x1440 297.0 1920 2064 2288 2640 1440 1441 1444 1500 -hsync +vsync
      1800x1440 230 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync
      1800x1440 250 1800 1896 2088 2392 1440 1441 1444 1490 +HSync +VSync
    640x480 @ 100.00 Hz (GTF) hsync: 50.90 kHz; pclk: 43.16 MHz 640x480 43.16 640 680 744 848 480 481 484 509 -HSync +Vsync
    768x576 @ 60.00 Hz (GTF) hsync: 35.82 kHz; pclk: 34.96 MHz 768x576 34.96 768 792 872 976 576 577 580 597 -HSync +Vsync
    768x576 @ 72.00 Hz (GTF) hsync: 43.27 kHz; pclk: 42.93 MHz 768x576 42.93 768 800 880 992 576 577 580 601 -HSync +Vsync
    768x576 @ 75.00 Hz (GTF) hsync: 45.15 kHz; pclk: 45.51 MHz 768x576 45.51 768 808 888 1008 576 577 580 602 -HSync +Vsync
    768x576 @ 85.00 Hz (GTF) hsync: 51.42 kHz; pclk: 51.84 MHz 768x576 51.84 768 808 888 1008 576 577 580 605 -HSync +Vsync
    768x576 @ 100.00 Hz (GTF) hsync: 61.10 kHz; pclk: 62.57 MHz 768x576 62.57 768 816 896 1024 576 577 580 611 -HSync +Vsync
    800x600 @ 100.00 Hz (GTF) hsync: 63.60 kHz; pclk: 68.18 MHz 800x600 68.18 800 848 936 1072 600 601 604 636 -HSync +Vsync
    1024x768 @ 100.00 Hz (GTF) hsync: 81.40 kHz; pclk: 113.31 MHz 1024x768 113.31 1024 1096 1208 1392 768 769 772 814 -HSync +Vsync
    1152x864 @ 60.00 Hz (GTF) hsync: 53.70 kHz; pclk: 81.62 MHz 1152x864 81.62 1152 1216 1336 1520 864 865 868 895 -HSync +Vsync
    1152x864 @ 85.00 Hz (GTF) hsync: 77.10 kHz; pclk: 119.65 MHz 1152x864 119.65 1152 1224 1352 1552 864 865 868 907 -HSync +Vsync
    1152x864 @ 100.00 Hz (GTF) hsync: 91.50 kHz; pclk: 143.47 MHz 1152x864 143.47 1152 1232 1360 1568 864 865 868 915 -HSync +Vsync
    1280x800 @ 60.00 Hz (GTF) hsync: 49.68 kHz; pclk: 83.46 MHz 1280x800 83.46 1280 1344 1480 1680 800 801 804 828 -HSync +Vsync
    1280x960 @ 72.00 Hz (GTF) hsync: 72.07 kHz; pclk: 124.54 MHz 1280x960 124.54 1280 1368 1504 1728 960 961 964 1001 -HSync +Vsync
    1280x960 @ 75.00 Hz (GTF) hsync: 75.15 kHz; pclk: 129.86 MHz 1280x960 129.86 1280 1368 1504 1728 960 961 964 1002 -HSync +Vsync
    1280x960 @ 100.00 Hz (GTF) hsync: 101.70 kHz; pclk: 178.99 MHz 1280x960 178.99 1280 1376 1520 1760 960 961 964 1017 -HSync +Vsync
    1280x1024 @ 100.00 Hz (GTF) hsync: 108.50 kHz; pclk: 190.96 MHz 1280x1024 190.96 1280 1376 1520 1760 1024 1025 1028 1085 -HSync +Vsync
    1368x768 @ 60.00 Hz (GTF) hsync: 47.70 kHz; pclk: 85.86 MHz 1368x768 85.86 1368 1440 1584 1800 768 769 772 795 -HSync +Vsync
    1400x1050 @ 60.00 Hz (GTF) hsync: 65.22 kHz; pclk: 122.61 MHz 1400x1050 122.61 1400 1488 1640 1880 1050 1051 1054 1087 -HSync +Vsync
    1400x1050 @ 72.00 Hz (GTF) hsync: 78.77 kHz; pclk: 149.34 MHz 1400x1050 149.34 1400 1496 1648 1896 1050 1051 1054 1094 -HSync +Vsync
    1400x1050 @ 75.00 Hz (GTF) hsync: 82.20 kHz; pclk: 155.85 MHz 1400x1050 155.85 1400 1496 1648 1896 1050 1051 1054 1096 -HSync +Vsync
    1400x1050 @ 85.00 Hz (GTF) hsync: 93.76 kHz; pclk: 179.26 MHz 1400x1050 179.26 1400 1504 1656 1912 1050 1051 1054 1103 -HSync +Vsync
    1400x1050 @ 100.00 Hz (GTF) hsync: 111.20 kHz; pclk: 214.39 MHz 1400x1050 214.39 1400 1512 1664 1928 1050 1051 1054 1112 -HSync +Vsync
    1440x900 @ 60.00 Hz (GTF) hsync: 55.92 kHz; pclk: 106.47 MHz 1440x900 106.47 1440 1520 1672 1904 900 901 904 932 -HSync +Vsync
    1600x1200 @ 100.00 Hz (GTF) hsync: 127.10 kHz; pclk: 280.64 MHz 1600x1200 280.64 1600 1728 1904 2208 1200 1201 1204 1271 -HSync +Vsync
    1680x1050 @ 60.00 Hz (GTF) hsync: 65.22 kHz; pclk: 147.14 MHz 1680x1050 147.14 1680 1784 1968 2256 1050 1051 1054 1087 -HSync +Vsync
    1920x1200 @ 60.00 Hz (GTF) hsync: 74.52 kHz; pclk: 193.16 MHz 1920x1200 193.16 1920 2048 2256 2592 1200 1201 1204 1242 -HSync +Vsync

    VGA timing information

    This documents tries to collect together information about standard VGA card timing details.


    Information form HP monitor manual


    Horizonal Timing

    Horizonal Dots         640     640     640         Vertical Scan Lines    350     400     480 Horiz. Sync Polarity   POS     NEG     NEG A (us)                 31.77   31.77   31.77     Scanline time B (us)                 3.77    3.77    3.77      Sync pulse lenght  C (us)                 1.89    1.89    1.89      Back porch D (us)                 25.17   25.17   25.17     Active video time E (us)                 0.94    0.94    0.94      Front porch
             ______________________          ________ ________|        VIDEO         |________| VIDEO (next line)     |-C-|----------D-----------|-E-| __   ______________________________   ___________   |_|                              |_|   |B|   |---------------A----------------|

    Vertical Timing

    Horizonal Dots         640     640     640 Vertical Scan Lines    350     400     480 Vert. Sync Polarity    NEG     POS     NEG       Vertical Frequency     70Hz    70Hz    60Hz O (ms)                 14.27   14.27   16.68     Total frame time P (ms)                 0.06    0.06    0.06      Sync length Q (ms)                 1.88    1.08    1.02      Back porch R (ms)                 11.13   12.72   15.25     Active video time S (ms)                 1.2     0.41    0.35      Front porch
             ______________________          ________ ________|        VIDEO         |________|  VIDEO (next frame)     |-Q-|----------R-----------|-S-| __   ______________________________   ___________   |_|                              |_|   |P|   |---------------O----------------|

    Informations source

    • HP D1194A Super VGA Display & HP D1195A Erognomic Super VGA Display Installation Guide, Hewlett Packard


    More VGA mode information

    There are the 3 "standard" VGA modes that each VGA card is supposed to be able to do:

    • 640 x 350 x 70 is compatible with the old EGA mode, but on a VGA display.

    • 640 x 400 x 70 is the MS-DOS text mode (when the computer is booting !).

    • 640 x 480 x 60 is the default Windows(tm) graphics mode (16 colours !).

    Their line frequency is exactly twice that of the NTSC television system, or almost twice that of the PAL television system. This makes it fairly easy to implement a VGA input on a television set that uses line doubling for the television signals so the line deflection already runs on 31 kHz.

    The following timings come from a list of 82 different computer timings, and by now there will be even more. Some video cards even have variable timing (allowing the user to set width, height and shift...). The only standard is that there is no standard !


    "640 x 350 (EGA on VGA)"    "640 x 400 VGA text"        "VGA industry standard" Clock frequency 25.175 MHz  Clock frequency 25.175 MHz  Clock frequency 25.175 MHz Line  frequency 31469 Hz    Line  frequency 31469 Hz    Line  frequency 31469 Hz Field frequency 70.086 Hz   Field frequency 70.086 Hz   Field frequency 59.94 Hz One line:                   One line:                   One line:   8 pixels front porch        8 pixels front porch        8 pixels front porch  96 pixels horizontal sync   96 pixels horizontal sync   96 pixels horizontal sync  40 pixels back porch        40 pixels back porch        40 pixels back porch   8 pixels left border        8 pixels left border        8 pixels left border 640 pixels video            640 pixels video            640 pixels video   8 pixels right border       8 pixels right border       8 pixels right border ---                         ---                         --- 800 pixels total per line   800 pixels total per line   800 pixels total per line
    One field:                  One field:                  One field:  31 lines front porch         5 lines front porch         2 lines front porch   2 lines vertical sync       2 lines vertical sync       2 lines vertical sync  54 lines back porch         28 lines back porch         25 lines back porch   6 lines top border          7 lines top border          8 lines top border 350 lines video             400 lines video             480 lines video   6 lines bottom border       7 lines bottom border       8 lines bottom border ---                         ---                         --- 449 lines total per field   449 lines total per field   525 lines total per field
    Sync polarity: H positive,  Sync polarity: H negative,  Sync polarity: H negative,                V negative                  V positive                  V negative Scan type: non interlaced.  Scan type: non interlaced.  Scan type: non interlaced.

    SuperVGA timing from NEC monitor manual

    Horizontal :                 ______________                 _____________                |              |               | _______________|  VIDEO       |_______________|  VIDEO (next line) ___________   _____________________   ______________________            |_|                     |_|             B C <------D-----><-E->             <----------A----------> Vertical :                 ______________                 _____________                |              |               |            _______________|  VIDEO       |_______________|  VIDEO (next frame) ___________   _____________________   ______________________            |_|                     |_|             P Q <------R-----><-S->             <----------O---------->

    For VESA 800*600 @ 60Hz:

    Fh (kHz) :37.88 A  (us)  :26.4 B  (us)  :3.2 C  (us)  :2.2 D  (us)  :20.0 E  (us)  :1.0 Fv (Hz)  :60.32 O  (ms)  :16.579 P  (ms)  :0.106 Q  (ms)  :0.607 R  (ms)  :15.84 S  (ms)  :0.026

    Timing used in one VGA monitor tester product

    The following timings are used in VTG-KIT VGA monitor tester kit sold my Data Sync Engineering.


    Mode       Horiz  Vertical  Horiz  Vert  Horiz  HSYNC  Vertical VSYNC            Dots   Lines     KHz    Hz    Sync   Pol    Sync     Pol VGA-480     640   480       31.5   60    3.8 us  -      64 us    - VGA-400     640   400       31.5   70    3.8 us  -      64 us    + SVGA I      800   600       35.2   56    2.0 us  -      57 us    - SVGA II     800   600       37.8   60    3.2 us  +     106 us    + SVGA III    800   600       48.0   72    2.4 us  +     125 us    + XGA        1024   768       48.5   60    2.0 us  -     124 us    -
    展开全文
  • 从RAM中提取因此不需要用到写使能,只需要读使能。此次用到的RAM中图片...VGA扫描一次为1/60HZ,当每扫n次换一副图片,这样就可以控制图片的转换速度 程序编写: module ram( input wire clk, input wire rst...
  • 新品上市 NCS8823:Type-C转VGA芯片介绍

    万次阅读 2018-03-05 12:05:19
    NCS8823 is a low-power and high performance Type-C Alt Mode 1.2 to VGA converter, designed to connect a USB Type-C source to a VGA sink. The NCS8823 integrates a DP1.2 compliant receiver, and a high-...
  • 之前学习了半年的图像处理,所以计划将自己学过的几个图像处理的基础算法,做过的设计记录下来,在OpenHW论坛上发表,计划是这样的,用VGA做显示,使用PC端上位机通过串口发送一幅图片数据到FPGA开发板,FPGA接收...
  • https://heiko-sieger.info/running-windows-10-on-linux-using-kvm-with-vga-passthrough virtual machines on a Linux host platform without compromising performance of the (Windows) guest system. For some ...
  • linux命令大全

    千次阅读 2015-12-24 08:44:14
    hwclock(hardware clock) 35 insmod(install module) 36 kbdconfig . 36 lilo(linux loader) 37 liloconfig . 38 lsmod(list modules) 38 minfo . 38 mkkickstart 39 modinfo...
  • NCS8823:TYPE-C to VGA Converter1 Features VGA Output Up to 1920x1080@60Hz supported Compliant with VESA VSIS 1.2 R/G/B swappable Load sensing 5V tolerance DD...
  • VmodCAM图像采集 VGA显示

    千次阅读 2014-06-12 17:25:03
    简单的VmodCAM图像采集 VGA显示
  • Piping OV7670 video to VGA output on ZYBO

    千次阅读 2016-08-11 15:59:47
    转自:http://lauri.xn–vsandi-pxa.com/hdl/zynq/zybo-ov7670-to-vga.htmlPiping OV7670 video to VGA output on ZYBO10. Nov ‘14IntroductionBefore getting into more complex topics such as AXI Stream and ...
  • 1 Features VGA Output Up to 1920x1200@60Hz supported DisplayPort Input Compliant with VESA DisplayPort 1.2 for 1.62Gbps/2.7Gbps Support DisplayPort 1/2 lanes 1Mbps AUX channel Ad...
  • VGA时序

    千次阅读 2013-06-04 17:47:47
    VGA Timings The following table lists timing values for several popular resolutions. Format Pixel Clock (MHz) Horizontal (in Pixels) Vertical (in Lines) Active Video Front Porch S
  • Altera University Program IP Core中有很多很受用的IP核,本人对其中的VGA核很感兴趣,却发现其并不是直接可用的(也许是我没找到),于是便写了个接口挂到了NiosII上。由于原例中在DE2开发板上实现,但其显存不能...
  • S04_CH01_搭建工程移植LINUX/测试EMMC/VGA 1.1概述: 本章内容是在已经提供安装了VIVADO2015.4 的ubuntu系统下,进行。大家可以下周我们已经提供的虚拟机镜像,我们提供的虚拟机镜像是安装了VIVADO的ubuntu系统,...
  • 友晶公司的5 Mega Pixel Digital Camera Development Kit(或者1.3Mega Pixel Digital Camera Development Kit )中的VGA_Controller核,它以SDRAM为显存,通过双端口SDRAM控制器从SDRAM中取数据从而写入VGA接口...
  • ov5640_mipi.c分析

    万次阅读 2016-08-24 13:04:22
    pr_err("%s: cannot get core voltage error\n", __func__); } analog_regulator = devm_regulator_get(dev, "AVDD"); if (!IS_ERR(analog_regulator)) { regulator_set_voltage(analog_regulator, ...
  • 랙덱클럭 - 램덱은 디지털신호를 아날로그로 바꿔주는 역할을 하며 클럭이 높을수록 선명한 화질을 표현해줌 코어클럭 - 초당 GPU가 연산하는 속...역할을 하는 핵심적인 칩셋으로 GPU 또는 코어라 함 core clock 核...
  • 在 Fedora Core 5 上体验 Aiglx 和 Xgl & Compiz(转)  摘要:  Aiglx是一个旨在为标准桌面启用GL加速功能的项目,目的在于通过小幅度修改X server、使用添加新协议支持...
  •  Some system manufacturers have similarly stated that their motherboards with Atom Cedarview processors lack 64-bit support due to a "lack of Intel® 64-bit VGA driver support". [24]  Because all  ...
  • Android内核的编译和调试

    万次阅读 2017-04-28 11:02:27
    localyesconfig - Update current config converting local mods to core silentoldconfig - Same as oldconfig, but quietly, additionally update deps defconfig - New config with default from ARCH ...
  • cd528028cc0649188c340d416b0f877d Virtualization: vmware Operating System: CentOS Linux 7 (Core) CPE OS Name: cpe:/o:centos:centos:7 Kernel: Linux 3.10.0-1160.el7.x86_64 Architecture: x86-64 [root@xyz...
  • 华为TaiShan 2280 ARM 服务器

    千次阅读 2019-02-13 18:09:00
    VGA compatible controller: Huawei Technologies Co., Ltd. Hi1710 [iBMC Intelligent Management system chip w /VGA support] (rev 01 ) (prog- if 00 [VGA controller]) Flags: bus master, fast devsel,...
  • linux内核文档汇集

    千次阅读 2019-09-09 09:18:57
    Software cursor for VGA Kernel Support for miscellaneous (your favourite) Binary Formats v1.1 Mono(tm) Binary Kernel Support for Linux Java(tm) Binary Kernel Support for Linux v1.03 ...
  • Radeon Gpu源码分析

    2021-04-16 20:50:48
    #endif if (drm_core_check_feature(dev, DRIVER_MODESET)) pci_set_drvdata(pdev, dev); drm_pci_agp_init(dev); ret = drm_dev_register(dev, ent->driver_data); if (ret) goto err_agp; /* No locking...
  • 显卡性能查看

    2020-08-07 09:39:55
    00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers (rev 08) 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) 00:04.0...
  • HDMI线、DP线或者HDMI转DVI线,实测HDMI转VGA会出现闪屏,不能使用 16G以上class 10或者更高级别Micro SD卡,并备好高速读卡器烧写镜像,个人使用的是128G的卡 网线、USB键盘和鼠标(网线连接到路由器,方便IP与...
  • VMware Workstation unrecoverable error: (vmx)

    万次阅读 2012-03-22 01:03:06
    As a result, the clock in your virtual machine may run too fast or too slow. Mar 22 00:38:46.044: vmx| Mar 22 00:38:46.044: vmx| For a workaround, please refer to the VMware knowledge base article ...

空空如也

空空如也

1 2 3 4 5 ... 20
收藏数 1,799
精华内容 719
关键字:

clockcorevga