• I'm trying to understand why we use generate in verilog along with a for loop.Using a generate and for loop together:reg [3:0] temp; genvar i; generate for (i = 0; i &lt; 3 ; i = i + 1) begin: ...
I'm trying to understand why we use generate in verilog along with a for loop.Using a generate and for loop together:reg [3:0] temp;
genvar i;
generate
for (i = 0; i < 3 ; i = i + 1) begin:
always @(posedge sysclk) begin
temp[i] <= 1'b0;
end
end
endgenerate
Using only for loop:reg [3:0] temp;
genvar i;
always @(posedge sysclk) begin
for (i = 0; i < 3 ; i = i + 1) begin:
temp[i] <= 1'b0;
end
end
I'm considering the two snippets would basically produce the same result i.e. temp[0] to temp[10] equal to value 0. What is the difference/advantage we see by using a generate statement in this case ?Answer1:In general, the main difference between generate for loop and regular for loop is that the generate for loop is generating an instance for each iteration. Meaning that in your example there will be 3 always blocks (as opposed to 1 block in the regular loop case).A good example of code that requires generate for is:module A();
..
endmodule;

module B();
parameter NUM_OF_A_MODULES = 2; // should be overriden from higher hierarchy
genvar i;
for (i=0 i<NUM_OF_A_MODULES; i=i+1) {
A A_inst();
}
endmodule;
In this example a regular for cannot do the work of creating NUM_OF_A_MODULES instances.In your example, you can acheive the required result in both ways. (as long as you fix some minor bugs :) )Answer2:Generate blocks are useful when change the physical structure of then module via parameters. For example choosing negedge or posedge clock and only enabling one:if ( param_use_pos == 1) begin : use_pos
always @(posedge sysclk) begin
...
end
end
else begin : use_neg
always @(negedge sysclk) begin
...
end
end
If you are not changing the physical structure, it is typically better to use for loops and if-else statements inside the always block. Both approaches can synthesize the same but when running RTL simulation the non-generate block approach will typically simulate faster. This is because simulators normally can process a single N-bit operation faster than N 1-bit operations. Again synthesis is the same result// faster :: 1 always block, simulator can optimize the for loop
always @(posedge sysclk) begin
for (i = 0; i < 3 ; i = i + 1) begin
temp[i] <= 1'b0;
end
end

// slower :: creates 4 always blocks, harder for the simulator to optimize
genvar i;
generate // optional if > *-2001
for (i = 0; i < 3 ; i = i + 1) begin
always @(posedge sysclk) begin
temp[i] <= 1'b0;
end
end
endgenerate // match generate
展开全文
• https://www.pythoncentral.io/how-to-use-pythons-xrange-and-range/ xrange() 函数用法与 range 完全相同，所不同是生成不是一个数组，而是一个生成器。 ... ...

https://www.pythoncentral.io/how-to-use-pythons-xrange-and-range/

xrange() 函数用法与 range 完全相同，所不同的是生成的不是一个数组，而是一个生成器。
http://www.runoob.com/python/python-func-xrange.html


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• make cmake 的区别学习 博客 博客地址：IT老兵驿站 正文 “The build process has one step if you use a Makefile, namely typing “make” at the command line. For CMake, there are two steps: First, you...
概要
make 和 cmake 的区别学习

博客
博客地址：IT老兵驿站
正文

“The build process has one step if you use a Makefile, namely typing “make” at the command line. For CMake, there are two steps: First, you need to setup your build environment (either by typing cmake <source_dir> in your build directory or by running some GUI client). This creates a makefile or something equivalent, depending on the build system of your choice (e.g. Make on *nix, VC++ or MinGW on Windows, etc). The build system can be passed to CMake as a parameter. However, CMake makes reasonable default choices depending on your system configuration. Second, you perform the actual build in the selected build system.”

参考上文所说，cmake 是两步，通过执行cmake <source_dir>（根据CMakeLists.txt文件的配置）， 先根据环境生成 Makefile 文件，然后正常使用 make 去进行编译。
传统的make，我这里的理解是通过configure去扫描软件的依赖，然后根据Makefile.in(往往是通过automake等工具所生成的)，生成Makefile。
cmake更多是帮助进行跨平台的编译。
初步理解是这样，等待以后来完善。
参考
https://www.quora.com/What-is-the-difference-between-CMake-and-make
https://prateekvjoshi.com/2014/02/01/cmake-vs-make/


展开全文
• is==的区别解释1 == is for value equality. Use it when you would like to know if two objects have the same value. is is for reference equality. Use it when you would like to know if two references ...
is和==的区别

解释1

== is for value equality. Use it when you would like to know if two objects have the same value.
is is for reference equality. Use it when you would like to know if two references refer to the same object.
解释2

is: if two variables point to the same object.
==: if the objects referred to by the variables are equal.
解释3

python中的每个对象都有三种属性：id, value, type.  不同对象实例的id一定是不同的，可以把id看做是和内存地址一一对应的。而value只是检查两个变量的内容是否相等。

解释4

== 会调用对应类里的__eq__()函数。例如：

class Name(object):
def __eq__(self, other):
print('__eq__() is called.')
name1 = Name()
name2 = Name()
print(name1  == name2)

结果：

__eq__() is called.
None    # __eq__()里面没有return，所以==的结果为None

然而如果没有重写__eq__()函数，我猜测就会去调用is的操作。例如：

class Name(object):
pass

# 创建两个不同的Name对象
name1 = Name()
name2 = Name()
# 让name3和name1指向同一个Name对象
name3 = name1

print(name1 is name2, name1  == name2)
print(name1 is name3, name1  == name3)

结果：

False False
True True

例外情况:

This is inconsistent with the earlier result. It turns out the reference implementation of Python caches integer objects in the range -5~256 as singleton instances for performance reasons.

Example:

for i in range(1, 10):
a = -i
is_res = a is int(str(a))
print("%i: %s" % (a, is_res))

print()

for i in range(250, 260):
a = i
is_res = a is int(str(a))
print("%i: %s" % (a, is_res))

results:

-1: True
-2: True
-3: True
-4: True
-5: True
-6: False
-7: False
-8: False
-9: False

250: True
251: True
252: True
253: True
254: True
255: True
256: True
257: False
258: False
259: False

参考：Is there a difference between == and is in Python?
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