Matcovnet 遇到了这个错误，查了资料才知道是filter的channel数目不对，查看手册发现：
 
 
 
 
 
 VL_NNCONV - CNN convolution.
 
 
 
 
 
 
 Y = VL_NNCONV(X, F, B) computes the convolution of the image X with the filter bank F and biases B. If B is the empty matrix, then no biases are added. If F is the empty matrix, then the function does not filter the image, but still adds the biases and applies downsampling and padding as explained below.
 
 
 
 
 X is an array of dimension H x W x C x N where (H,W) are the height and width of the image stack, C is the number of feature channels, and N is the number of images in the batch.
 
 
 
 
 F is an array of dimension FW x FH x FC x K where (FH,FW) are the filter height and width and K the number o filters in the bank. FC is the number of feature channels in each filter and must match the number of feature channels C in X. Alternatively, FC can
 
 divide* the C; in this case, filters are assumed to form G=C/FC
 groups* of equal size (where G must divide K). Each group of 
 
 
 
 filters works on a consecutive subset of feature channels of the input array X.
 
 
黑色的是重点，要求FC与C关系，不然会报错。
 
这个提问，可以参考下。
 
https://github.com/vlfeat/matconvnet/issues/222
 
 
 
 Hi, your data has 384 channels, and your filters only one channel. This means that there are 384 filter groups, one for each channel, and each containing one filter. If this is your intention, you should have 384 filters, each of which will act independently on a corresponding input dimension (note that working with many small groups is not implemented very efficiently in the library).
 
 However, I think you meant to create filters with 384 dimensions instead. If this is the case the filters should be randn(7,7,384,50, 'single’).
 
 
 
On 29 Jul 2015, at 11:16, Kevin Chen notifications@github.com wrote:
 
 
Hi, guys. In my implementation, the first layer was displayed for error using : the number of filter groups does not divide the total number of filters. So I wondered why I got this error message. Can anyone help me out? Thanks a lot.
 
 
% layer 1: convolution
 net.layers{end+1} = struct('type', 'conv', ...
 'filters', f*randn(7,7,1,50, 'single'), ...
 'biases', zeros(1, 50,'single'), ...
 'stride', 1, ...
 
 
'pad', 0) ;
 
 
l.filters =
 
 
7 7 1 50
 l.biases =
 
 
1 50
 res(i).x =
 .
 
 
32 32 384 100
 
 
Error using vl_nnconv
 The number of filter groups does not divide the total number of filters.
 
 
Error in vl_simplenn (line 156)
 res(i+1).x = vl_nnconv(res(i).x, l.filters, l.biases, 'pad', l.pad, 'stride', l.stride) ;
 
 
Error in cnn_train (line 141)
 res = vl_simplenn(net, im, one, res, ...
 
 
Error in cnn_LIVEII (line 93)
 [net,info] = cnn_train(net, imdb, @getbatch, ... % "net" with above-defined layers
 
 
—
 Reply to this email directly or view it on GitHub #222.
 
 

Number of Bank Machines:
 DDR3 IP设置中会要求设置ddr3的bank数量，让人困惑的是此前已经选择了确定的器件，bank数量是固定的，为什么这里让选择bank的数量呢？
 Xilinx官网有一条类似的问题被解决：
 提问者：
 I’m designing with the DDR3 IP core and using the Wizard to configure the memory.
 I have selected the Memory Type = SODIMM and have supplied the memory part number.
 One of the Wizard page ask to define the “Number of BANK machine”
 Is this the same as the Bank address for the DDR3? If my DDR3 SODIMM datasheet has defined bank address(2:0)
 then should I select from the Wizard for “Number of Bank Address” = 8 ?
 Since the memory Part# is supplied to the Wizard already, why do I have to supply this Number of Bank Address?
 Or is the Wizard asking for something else instead, seem like it means something else and not referring to the Bank address, not sure… …confusing.
 官网回答：
 Yes, the number of Bank Machines corresponds to the banks of the DDR3 device.
 The IP usually defaults to 4 for larger devices and sometimes less for smaller devices. The reason it defaults to 4 is because adding more bank machines uses more FPGA resources which means you could have issues fitting the design and closing timing depending on your device and how full it is. For most applications users are able to high performance out of the MIG with 4 bank machines when they consider how to efficiently address the MIG through the app_addr and the “Memory Address Mapping Selection.” Some users may have a more bursty and random access pattern where they could see efficiency improvements with more bank machines, but other times some customers see no benefit from more bank machines but used more FPGA resources and didn’t see any benefit. My recommendation is to run simulations to see if you need or benefit from more bank machines.
 UG586 talks about this starting on page 123.
 
可以看出这个选项的目的是为了使用ddr3ip时节省FPGA的资源。
 更多信息可以查看原对话：
 地址为
 https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/DDR3-IP-Number-of-Bank-Machine/m-p/900013