• 名称:并行数据转换为串行数据 说 明 : 切 换 连 接 到 并 串 转 换 芯 片74LS165 的拨码开关,该芯片将并行数据以串行方式发送到 8051 的 RXD 引脚,移位脉冲由 TXD 提供,显示在 P0 口。
  • 并行传输数据和串行传输数据SATA hard drive connections are faster than older PATA hard drive connections and the same can be said for external cabling standards, but this is counter-intuitive: why ...


    SATA hard drive connections are faster than older PATA hard drive connections and the same can be said for external cabling standards, but this is counter-intuitive: why wouldn’t the parallel transmission be faster?


    Today’s Question & Answer session comes to us courtesy of SuperUser—a subdivision of Stack Exchange, a community-driven grouping of Q&A web sites.

    今天的“问答”环节由SuperUser提供,它是Stack Exchange的一个分支,该社区是由社区驱动的Q&A网站分组。

    问题 (The Question)

    SuperUser reader Modest is curious about the data transfer rates of parallel and serial connections:


    Intuitively, you would think that parallel data transmission should be faster than serial data transmission; in parallel you are transferring many bits at the same time, whereas in serial you are doing one bit at a time.

    凭直觉,您会认为并行数据传输应该比串行数据传输快; 并行操作是同时传输许多位,而串行操作是一次传输一位。

    So what makes SATA interfaces faster than PATA, PCI-e devices faster than PCI, and serial ports faster than parallel?


    While it’s easy to fall into the reasoning that SATA is newer than PATA, there must be a more concrete mechanism at work than just age.


    答案 (The Answer)

    SuperUser contributor Mpy offers some insight into the nature of the transmission types:


    You cannot formulate it this way.


    Serial transmission is slower than parallel transmission given the same signal frequency. With a parallel transmission you can transfer one word per cycle (e.g. 1 byte = 8 bits) but with a serial transmission only a fraction of it (e.g. 1 bit).

    相同的信号频率下,串行传输比并行传输要慢 在并行传输中,您可以每个周期传输一个字(例如1字节= 8位),而在串行传输中,仅传输其一小部分(例如1位)。

    The reason modern devices use serial transmission is the following:


    • You cannot increase the signal frequency for a parallel transmission without limit, because, by design, all signals from the transmitter need to arrive at the receiver at the same time. This cannot be guaranteed for high frequencies, as you cannot guarantee that the signal transit time is equal for all signal lines (think of different paths on the mainboard). The higher the frequency, the more tiny differences matter. Hence the receiver has to wait until all signal lines are settled — obviously, waiting lowers the transfer rate.

      您可以在不增加信号频率并行传输无极限,因为按照设计,从发射器需要的所有信号在接收器在同一时间到达。 这不能保证在高频下使用,因为您不能保证所有信号线的信号传输时间都相等(请考虑主板上的不同路径)。 频率越高,差异越小。 因此,接收器必须等到所有信号线都建立好之后,显然,等待会降低传输速率。

    • Another good point (from this post) is that one needs to consider crosstalk with parallel signal lines. The higher the frequency, the more pronounced crosstalk gets and with it the higher the probability of a corrupted word and the need to retransmit it. [1]

      另一个好处(来自本文)是,需要考虑与并行信号线的串扰。 频率越高,串扰越明显,随之而来的单词损坏和重传的可能性也越高。 [1]

    So, even if you transfer less data per cycle with a serial transmission, you can go to much higher frequencies which results in a higher net transfer rate.


    [1] This also explains why UDMA-Cables (Parallel ATA with increased transfer speed) had twice as many wires as pins. Every second wire was grounded to reduce crosstalk.

    [1]这也解释了为什么UDMA电缆(具有更高传输速度的并行ATA)的导线数是引脚的两倍。 每隔两根导线接地,以减少串扰。

    Scott Chamberlain echoes Myp’s answer and expands upon the economics of design:

    斯科特·张伯伦(Scott Chamberlain)回应了Myp的回答,并扩展了设计经济学:

    The problem is synchronization.


    When you send in parallel you must measure all of the lines at the exact same moment, as you go faster the size of the window for that moment gets smaller and smaller, eventually it can get so small that some of the wires may still be stabilizing while others are finished before you ran out of time.


    By sending in serial you no longer need to worry about all of the lines stabilizing, just one line. And it is more cost efficient to make one line stabilize 10 times faster than to add 10 lines at the same speed.

    通过串行发送,您无需担心所有线路都稳定下来,只需担心一条线路。 而且,使一条线的稳定速度比以相同速度添加10条线的速度快10倍,具有更高的成本效益。

    Some things like PCI Express do the best of both worlds, they do a parallel set of serial connections (the 16x port on your motherboard has 16 serial connections). By doing that each line does not need to be in perfect sync with the other lines, just as long as the controller at the other end can reorder the “packets” of data as they come in using the correct order.

    诸如PCI Express之类的东西在两全其美方面发挥了最大作用,它们完成了一组并行的串行连接(主板上的16x端口具有16个串行连接)。 通过这样做,只要另一端的控制器可以按照正确的顺序对数据的“数据包”进行重新排序,就不必与其他行完美同步。

    The How Stuff Works page for PCI-Express does a very good explination in depth on how PCI Express in serial can be faster than PCI or PCI-X in parallel.

    PCI-Express的“工作原理”页面对串行PCI Express如何比并行PCI或PCI-X更快提供了很好的深度解释。

    TL;DR Version: It is easier to make a single connection go 16 times faster than 8 connections go 2 times faster once you get to very high frequencies.

    TL; DR版本:一旦到达非常高的频率,使单个连接的传输速度比8个连接的传输速度快2倍就容易了。

    Have something to add to the explanation? Sound off in the the comments. Want to read more answers from other tech-savvy Stack Exchange users? Check out the full discussion thread here.

    有什么补充说明吗? 在评论中听起来不对。 是否想从其他精通Stack Exchange的用户那里获得更多答案? 在此处查看完整的讨论线程

    翻译自: https://www.howtogeek.com/171947/why-is-serial-data-transmission-faster-than-parallel-data-transmission/


  • 并行传输数据和串行传输数据 计算机系统中的并行处理和数据传输模式 (Parallel Processing and Data Transfer Modes in a Computer System) Instead of processing each instruction sequentially, a parallel ...


    Instead of processing each instruction sequentially, a parallel processing system provides concurrent data processing to increase the execution time.


    In this the system may have two or more ALU's and should be able to execute two or more instructions at the same time. The purpose of parallel processing is to speed up the computer processing capability and increase its throughput.

    在这种情况下,系统可能具有两个或多个ALU,并且应该能够同时执行两个或多个指令。 并行处理的目的是加快计算机处理能力并提高其吞吐量。

    NOTE: Throughput is the number of instructions that can be executed in a unit of time.

    注意: 吞吐量是单位时间内可以执行的指令数。

    Parallel processing can be viewed from various levels of complexity. At the lowest level, we distinguish between parallel and serial operations by the type of registers used. At the higher level of complexity, parallel processing can be achieved by using multiple functional units that perform many operations simultaneously.

    可以从各种复杂度上查看并行处理。 在最低层次上,我们通过使用的寄存器类型区分并行操作和串行操作。 在较高的复杂度上,可以通过使用同时执行许多操作的多个功能单元来实现并行处理。

    Mapping and Concept of Virtual Memory

    计算机系统的数据传输模式 (Data Transfer Modes of a Computer System)

    According to the data transfer mode, computer can be divided into 4 major groups:


    1. SISD


    2. SIMD


    3. MISD


    4. MIMD


    SISD(单指令流,单数据流) (SISD (Single Instruction Stream, Single Data Stream))

    It represents the organization of a single computer containing a control unit, processor unit and a memory unit. Instructions are executed sequentially. It can be achieved by pipelining or multiple functional units.

    它代表了包含控制单元,处理器单元和存储单元的单个计算机的组织。 指令按顺序执行。 可以通过流水线或多个功能单元来实现。

    SIMD(单指令流,多数据流) (SIMD (Single Instruction Stream, Multiple Data Stream))

    It represents an organization that includes multiple processing units under the control of a common control unit. All processors receive the same instruction from control unit but operate on different parts of the data.

    它代表一个组织,在一个公共控制单元的控制下包括多个处理单元。 所有处理器都从控制单元接收相同的指令,但是对数据的不同部分进行操作。

    They are highly specialized computers. They are basically used for numerical problems that are expressed in the form of vector or matrix. But they are not suitable for other types of computations

    它们是高度专业的计算机。 它们基本上用于以向量或矩阵形式表示的数值问题。 但是它们不适合其他类型的计算

    MISD(多指令流,单数据流) (MISD (Multiple Instruction Stream, Single Data Stream))

    It consists of a single computer containing multiple processors connected with multiple control units and a common memory unit. It is capable of processing several instructions over single data stream simultaneously. MISD structure is only of theoretical interest since no practical system has been constructed using this organization.

    它由一台计算机组成,其中包含与多个控制单元和一个公共存储单元连接的多个处理器。 它能够同时在单个数据流上处理多个指令。 MISD结构仅具有理论意义,因为尚未使用该组织构建实用系统。

    MIMD(多指令流,多数据流 (MIMD (Multiple Instruction Stream, Multiple Data Stream)

    It represents the organization which is capable of processing several programs at same time. It is the organization of a single computer containing multiple processors connected with multiple control units and a shared memory unit. The shared memory unit contains multiple modules to communicate with all processors simultaneously. Multiprocessors and multicomputer are the examples of MIMD. It fulfills the demand of large scale computations.

    它代表能够同时处理多个程序的组织。 它是一台计算机的组织,其中包含与多个控制单元和一个共享存储单元连接的多个处理器。 共享内存单元包含多个模块,可同时与所有处理器通信。 多处理器和多计算机是MIMD的示例。 它满足了大规模计算的需求。

    翻译自: https://www.studytonight.com/computer-architecture/parallel-processing-and-data-transfer


  • 用于串行数据并行数据的VHDL代码,可参考,欢迎下载
  • 并行数据转换为串行数据_74ls165 由拨马开关控制并行数据状态,通过74LS165转串口输出 在由8位LED灯的亮灭来显示当前的拨码开关的状态 源程序+Proteus的仿真文件 可以帮助你很好的学习哦
  • 名称:串行数据转换为并行数据 说明:串行数据由 RXD 发送给串 并转换芯片 74164,TXD 则用于输出移位时钟脉冲,74164 将串行输入的 1 字节转换为并行数据,并将转换的数据通过 8 只 LED 显示出来。本例串口工作...
  • //进来的数据和使能打两拍同步一下 always@(posedge clk_50M_i or negedge rst_n_i) if(!rst_n_i)begin data_i_tmp1 ; data_i_tmp2 ; data_en_tmp1 ; data_en_tmp2 ; end else begin data_i_tmp1 ; ...


    module bit4_bit1(
        input    clk_50M_i,
    	input    rst_n_i,
    	input    [3:0]data_i,
    	input    data_en_i,
    	output   data_o,
    	output   data_en_o
    reg    [3:0]data_i_tmp1;
    reg    [3:0]data_i_tmp2;
    reg    [3:0]data_i_valid;
    reg         data_en_tmp1;
    reg         data_en_tmp2;
    reg    [3:0]cnt;
    reg  data_o_tmp;
    reg  data_en_o_tmp;
    always@(posedge clk_50M_i or negedge rst_n_i)
    	    data_i_tmp1    <= 4'b0;
    		data_i_tmp2    <= 4'b0;
    		data_en_tmp1   <= 1'b0;
    		data_en_tmp2   <= 1'b0;
    	else  begin
    	    data_i_tmp1    <= data_i;
    		data_i_tmp2    <= data_i_tmp1;
    		data_en_tmp1   <= data_en_i;
    		data_en_tmp2   <= data_en_tmp1;
    always@(posedge clk_50M_i or negedge rst_n_i)
    	    data_i_valid <= 4'b0;
    	else if(data_en_tmp2)
    	    data_i_valid <= data_i_tmp2;
    	    data_i_valid <= data_i_valid;
    always@(posedge clk_50M_i or negedge rst_n_i)
    	    cnt <= 4'b0;
    	else if(data_en_tmp2 || (cnt>0&&cnt<4))
    	    cnt <= cnt + 1'b1;
    	    cnt <= 4'b0;
    always@(posedge clk_50M_i or negedge rst_n_i)
    	    data_o_tmp <= 1'b0;
    	else if(cnt!=0)
    	    data_o_tmp <= data_i_valid[4-cnt];
    	    data_o_tmp <= 1'b0;
    always@(posedge clk_50M_i or negedge rst_n_i)
    	    data_en_o_tmp <= 1'b0;
    	else if(cnt!=0)
    	    data_en_o_tmp <= 1'b1;
    	    data_en_o_tmp <= 1'b0;
    assign  data_o = data_o_tmp;
    assign  data_en_o = data_en_o_tmp;


    `timescale 1ns/1ns
    module  bit4_bit1_tb();
    parameter  clk_period = 20;
    reg    clk_50M_i;
    reg    rst_n_i;
    reg    [3:0]data_i;
    reg    data_en_i;
    initial begin
            clk_50M_i = 1'b0;
            rst_n_i   = 1'b0;
    	data_i = 4'b0000;
            data_en_i = 1'b0;
    	rst_n_i = 1'b1;
    	data_i = 4'b0001;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0010;        
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0011;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0100;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0101;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0110;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0111;
             data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b1000;
            data_en_i = 1'b1;
            #clk_period  data_en_i = 1'b0;
    	data_i = 4'b0;
    always #(clk_period/2) clk_50M_i = ~clk_50M_i;
    bit4_bit1  bit4_bit1_inst(


  • 串行和并行

    千次阅读 2019-07-31 19:21:31
    串行传输:串行传输即串行通信,是指使用一条数据线 将数据一位一位地依次传输,每一个数据占据一个固定的时间长度,其只需要少数几条线就可以在系统之间交换信息,特别适合计算机计算机 计算机外设之间的远距离...

    串行传输:串行传输即串行通信,是指使用一条数据线 将数据一位一位地依次传输,每一个数据占据一个固定的时间长度,其只需要少数几条线就可以在系统之间交换信息,特别适合计算机和计算机  计算机和外设之间的远距离通信。









  • 单片机并行数据转换为串行数据,比赛练习案例,仿真实例,现成调用封装使用,可运行的仿真电路图调好的程序,开箱即用。适用于教学案例、毕业设计、电子设计比赛、出书项目实例,实际设计、个人DIY参考。 已调试好...
  • 并行数据串行数据模块的设计

    千次阅读 2017-11-14 19:08:59
    通信协议 scl为不断输出的时钟信号,如果scl为高电平时...如果scl为高电平,sda由低变高,串行数据结束。sda信号的数据值必须在scl高电平之间稳定,在scl低电平时才可以改变,否则的话,立即就结束了串行数据的转换。
  • 单片机串行数据转换为并行数据,比赛练习案例,仿真实例,现成调用封装使用,可运行的仿真电路图调好的程序,开箱即用。适用于教学案例、毕业设计、电子设计比赛、出书项目实例,实际设计、个人DIY参考。 已调试好...
  • endmodule 仿真截图: 说明:无意中看到了一些博客上的数据串并转换,逻辑上基本都能实现,但绝大部分都不能用,连基本的信号使能、时序打拍都没有,信号命名也很随便,就简单的实现了移位寄存器,直接复用的价值...
  • 模块功能:接收串行数据,转为并行数据。 应用场景:在SPI,Uart等串行协议接收侧均有应用。 二. 模块框图与使用说明 有两种模式(通过参数SDATA_IS_CONTINUOUS进行选择): 1.数据连续模式,此时sdata_valid指示...
  • 设计两个可综合的电路模块:第一个模块(M1)接受四位并行数据,并将其转化为简化I2C传输格式。sclk为输入主钟,data[3:0]为输入的四位数据,ack为请求发送数据信号(请求后才有数据发送到data[3:0]),数据流用scl...
  • 串行数据并行数据并行数据串行数据行转串行代码 module parallel_to_serial(clk,data_in,data_out,state); input clk;input [7:0] data_in;output data_out;output [7:0] state;reg [7:0] state=0;reg data_...
  • protues串行数据转换为并行数据很经典。
  • 并行数据转换为串行数据的转换器

    万次阅读 2017-07-24 12:04:16
    这篇文章写一下今天早上设计的并行数据串行数据的转换器,也算是对并行总线串行总线一个小小的应用,编码过程中也用到了task。 该转换器主要实现的功能是: 1、把并行地址存入寄存器 2、把并行数据存入寄存器 3...
  • 并行串行 串行并行输出模块

    千次阅读 2018-12-28 17:50:02
    并行转串行 串行转并行输出模块 夏宇闻Verilog 第15章学习笔记 通信协议:scl为高,sda由高跳变低,start;scl为高,sda由低跳变为高,stop;scl为低,sda数据位才能...//************************并行数据转一种...
  • 利用单片机的串行I/O 端口串行输出,利用74LS164移位转换成并行数据,接在LED灯上显示。74LS164置于通用插座上。
  • 串行和并行的区别

    千次阅读 2017-02-09 09:13:40
    并行与串行 分类:默认栏目计算机系统的信息交换有两种方式:并行数据传输方式和串行数据传输方式。并行数据传输是以计算机的字长,通常是8位、16位、32位为传输单位,一次传送一个字长的数据。它适合于外部设备与CPU...
  • 源代码+仿真+电路图
  • 并行和串行

    万次阅读 多人点赞 2019-04-07 15:08:26
    并行和串行都是通讯中数据传输的方式,二者有着本质的不同。 1.并行通讯:同一时刻,可以传输多个bit位的信号,有多少个信号位就需要多少根信号线。 2.串行通讯:同一时刻,只能传输一个bit位的信号,只需要一根...
  • 串行和并行接口模式是A/D转换器诸多分类中的一种,但却是应用中器件选择的一个重要指标。在同样的转换分辨率及转换速度的前提下,不同的接口方式不但影响了电路结构,更重要的是将在高速数据采集的过程中对采样周期...
  • 摘要:串行和并行接口模式是A/D转换器诸多分类中的一种,但却是应用中器件选择的一个重要指标。在同样的转换分辨率及转换速度的前提下,不同的接口方式不但影响了电路结构,更重要的是将在高速数据采集的过程中对...
  • 摘 要:根据高速定点DSP芯片TMS320VC5402的多通道缓冲串口特点和串行A/D转换芯片TLV1572的工作特性,提出了两片串行A/D一片DSP串口的通信方案。该系统充分利用了DSP的两个缓冲串口,可以使两路A/D转换数据高速并行...
  • 74HC595 - 串行并行

    2020-07-14 17:44:36
    1)SHIFT CLOCK:移位时钟输入引脚,上升沿将数据串行输入; 2)SERIAL DATA INPUT:串行数据输入引脚; 3)RESET:清空移位寄存器中数据,低电平有效; 4)LATCH CLOCK:锁存寄存器时钟输入引脚,上升沿将数据完成锁存; 5)...
  • 串行数据输入信号din。 输出信号为8bit并行信号dout。 每经过8个时钟周期,便把收到的8个串行信号合成并行信号并输出,等下8个时钟周期过后再输出下一个并行信号。 module deserialize( input rst,clk,din, output ...
  • 源代码+仿真+电路图
  • ad7606模块8通道,ad7606模块程序并行方式采集



1 2 3 4 5 ... 20
收藏数 116,930
精华内容 46,772